| 1 | From af14a456c58c153c6d761e6c0af48157692b52ad Mon Sep 17 00:00:00 2001 |
| 2 | From: John Crispin <blogic@openwrt.org> |
| 3 | Date: Fri, 9 Nov 2012 13:43:30 +0100 |
| 4 | Subject: [PATCH 5/6] MIPS: lantiq: adds code for booting GPHY |
| 5 | |
| 6 | The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to |
| 7 | boot them up. |
| 8 | |
| 9 | Signed-off-by: John Crispin <blogic@openwrt.org> |
| 10 | Patchwork: http://patchwork.linux-mips.org/patch/4522 |
| 11 | --- |
| 12 | .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 ++ |
| 13 | arch/mips/lantiq/xway/reset.c | 36 ++++++++++++++++++++ |
| 14 | 2 files changed, 39 insertions(+) |
| 15 | |
| 16 | diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h |
| 17 | index 6a2df70..133336b 100644 |
| 18 | --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h |
| 19 | +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h |
| 20 | @@ -82,6 +82,9 @@ extern __iomem void *ltq_cgu_membase; |
| 21 | #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) |
| 22 | #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) |
| 23 | |
| 24 | +/* allow booting xrx200 phys */ |
| 25 | +int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr); |
| 26 | + |
| 27 | /* request a non-gpio and set the PIO config */ |
| 28 | #define PMU_PPE BIT(13) |
| 29 | extern void ltq_pmu_enable(unsigned int module); |
| 30 | diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c |
| 31 | index 2799212..544dbb7 100644 |
| 32 | --- a/arch/mips/lantiq/xway/reset.c |
| 33 | +++ b/arch/mips/lantiq/xway/reset.c |
| 34 | @@ -28,9 +28,15 @@ |
| 35 | #define RCU_RST_REQ 0x0010 |
| 36 | /* reset status register */ |
| 37 | #define RCU_RST_STAT 0x0014 |
| 38 | +/* vr9 gphy registers */ |
| 39 | +#define RCU_GFS_ADD0_XRX200 0x0020 |
| 40 | +#define RCU_GFS_ADD1_XRX200 0x0068 |
| 41 | |
| 42 | /* reboot bit */ |
| 43 | +#define RCU_RD_GPHY0_XRX200 BIT(31) |
| 44 | #define RCU_RD_SRST BIT(30) |
| 45 | +#define RCU_RD_GPHY1_XRX200 BIT(29) |
| 46 | + |
| 47 | /* reset cause */ |
| 48 | #define RCU_STAT_SHIFT 26 |
| 49 | /* boot selection */ |
| 50 | @@ -60,6 +66,36 @@ unsigned char ltq_boot_select(void) |
| 51 | return RCU_BOOT_SEL(val); |
| 52 | } |
| 53 | |
| 54 | +/* reset / boot a gphy */ |
| 55 | +static struct ltq_xrx200_gphy_reset { |
| 56 | + u32 rd; |
| 57 | + u32 addr; |
| 58 | +} xrx200_gphy[] = { |
| 59 | + {RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200}, |
| 60 | + {RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200}, |
| 61 | +}; |
| 62 | + |
| 63 | +/* reset and boot a gphy. these phys only exist on xrx200 SoC */ |
| 64 | +int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr) |
| 65 | +{ |
| 66 | + if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) { |
| 67 | + dev_err(dev, "this SoC has no GPHY\n"); |
| 68 | + return -EINVAL; |
| 69 | + } |
| 70 | + if (id > 1) { |
| 71 | + dev_err(dev, "%u is an invalid gphy id\n", id); |
| 72 | + return -EINVAL; |
| 73 | + } |
| 74 | + dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr); |
| 75 | + |
| 76 | + ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | xrx200_gphy[id].rd, |
| 77 | + RCU_RST_REQ); |
| 78 | + ltq_rcu_w32(dev_addr, xrx200_gphy[id].addr); |
| 79 | + ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~xrx200_gphy[id].rd, |
| 80 | + RCU_RST_REQ); |
| 81 | + return 0; |
| 82 | +} |
| 83 | + |
| 84 | /* reset a io domain for u micro seconds */ |
| 85 | void ltq_reset_once(unsigned int module, ulong u) |
| 86 | { |
| 87 | -- |
| 88 | 1.7.10.4 |
| 89 | |
| 90 | |
