| 1 | From d8d9b9055d704d6f84ef6346d6826b8a9640f209 Mon Sep 17 00:00:00 2001 |
| 2 | From: John Crispin <blogic@openwrt.org> |
| 3 | Date: Mon, 22 Oct 2012 10:25:39 +0200 |
| 4 | Subject: [PATCH 112/123] MTD: lantiq: xway: fix NAND reset timeout handling |
| 5 | |
| 6 | Fixes a possible deadlock in the code that resets the NAND flash. |
| 7 | |
| 8 | http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html |
| 9 | |
| 10 | Signed-off-by: John Crispin <blogic@openwrt.org> |
| 11 | --- |
| 12 | drivers/mtd/nand/xway_nand.c | 12 ++++++++++-- |
| 13 | 1 file changed, 10 insertions(+), 2 deletions(-) |
| 14 | |
| 15 | diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c |
| 16 | index 3f81dc8..4731300 100644 |
| 17 | --- a/drivers/mtd/nand/xway_nand.c |
| 18 | +++ b/drivers/mtd/nand/xway_nand.c |
| 19 | @@ -58,15 +58,23 @@ static void xway_reset_chip(struct nand_chip *chip) |
| 20 | { |
| 21 | unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W; |
| 22 | unsigned long flags; |
| 23 | + unsigned long timeout; |
| 24 | |
| 25 | nandaddr &= ~NAND_WRITE_ADDR; |
| 26 | nandaddr |= NAND_WRITE_CMD; |
| 27 | |
| 28 | /* finish with a reset */ |
| 29 | + timeout = jiffies + msecs_to_jiffies(200); |
| 30 | + |
| 31 | spin_lock_irqsave(&ebu_lock, flags); |
| 32 | + |
| 33 | writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr); |
| 34 | - while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) |
| 35 | - ; |
| 36 | + do { |
| 37 | + if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) |
| 38 | + break; |
| 39 | + cond_resched(); |
| 40 | + } while (!time_after_eq(jiffies, timeout)); |
| 41 | + |
| 42 | spin_unlock_irqrestore(&ebu_lock, flags); |
| 43 | } |
| 44 | |
| 45 | -- |
| 46 | 1.7.10.4 |
| 47 | |
| 48 | |
