| 1 | /* |
| 2 | * mcs8140.dtsi - Device Tree Include file for Moschip MCS8140 family SoC |
| 3 | * |
| 4 | * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org> |
| 5 | * |
| 6 | * Licensed under GPLv2. |
| 7 | */ |
| 8 | |
| 9 | /include/ "skeleton.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "Moschip MCS8140 family SoC"; |
| 13 | compatible = "moschip,mcs8140"; |
| 14 | interrupt-parent = <&intc>; |
| 15 | |
| 16 | aliases { |
| 17 | serial0 = &uart0; |
| 18 | eth0 = ð0; |
| 19 | }; |
| 20 | |
| 21 | cpus { |
| 22 | cpu@0 { |
| 23 | compatible = "arm,arm926ejs"; |
| 24 | }; |
| 25 | }; |
| 26 | |
| 27 | ahb { |
| 28 | compatible = "simple-bus"; |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <1>; |
| 31 | ranges; |
| 32 | |
| 33 | vci { |
| 34 | compatible = "simple-bus"; |
| 35 | #address-cells = <1>; |
| 36 | #size-cells = <1>; |
| 37 | ranges; |
| 38 | |
| 39 | eth0: ethernet@40084000 { |
| 40 | compatible = "moschip,nuport-mac"; |
| 41 | reg = <0x40084000 0xd8 // mac |
| 42 | 0x40080000 0x58>; // dma channels |
| 43 | interrupts = <4 5 29>; /* tx, rx, link */ |
| 44 | nuport-mac,buffer-shifting; |
| 45 | nuport-mac,link-activity = <0>; |
| 46 | }; |
| 47 | |
| 48 | tso@40088000 { |
| 49 | reg = <0x40088000 0x1c>; |
| 50 | interrupts = <7>; |
| 51 | }; |
| 52 | |
| 53 | i2s@4008c000 { |
| 54 | compatible = "moschip,mcs814x-i2s"; |
| 55 | reg = <0x4008c000 0x18>; |
| 56 | interrupts = <8>; |
| 57 | }; |
| 58 | |
| 59 | ipsec@40094000 { |
| 60 | compatible = "moschip,mcs814x-ipsec"; |
| 61 | reg = <0x40094000 0x1d8>; |
| 62 | interrupts = <16>; |
| 63 | }; |
| 64 | |
| 65 | rng@4009c000 { |
| 66 | compatible = "moschip,mcs814x-rng"; |
| 67 | reg = <0x4009c000 0x8>; |
| 68 | }; |
| 69 | |
| 70 | memc@400a8000 { |
| 71 | reg = <0x400a8000 0x58>; |
| 72 | }; |
| 73 | |
| 74 | list-proc@400ac0c0 { |
| 75 | reg = <0x400ac0c0 0x38>; |
| 76 | interrupts = <19 27>; // done, error |
| 77 | }; |
| 78 | |
| 79 | pci@400b0000 { |
| 80 | compatible = "moschip,mcs8140-pci", "moschip,mcs814x-pci"; |
| 81 | reg = <0x400b0000 0x44 // PCI master |
| 82 | 0x400d8000 0xe4>; // EEPROM emulator |
| 83 | interrupts = <25>; // abort interrupt |
| 84 | status = "disabled"; |
| 85 | #address-cells = <3>; |
| 86 | #size-cells = <2>; |
| 87 | |
| 88 | ranges = <0x01000000 0 0x80000000 0x80000000 0 0x04000000 // IO |
| 89 | 0x42000000 0 0x90000000 0x90000000 0 0x20000000 // non-prefetch |
| 90 | 0x02000000 0 0xb0000000 0xb0000000 0 0x10000000>; // prefecth |
| 91 | |
| 92 | #interrupt-cells = <1>; |
| 93 | interrupt-map-mask = <>; |
| 94 | interrupt-map = <0 0 0 1 &intc 22 0 |
| 95 | 0 0 0 2 &intc 23 0 |
| 96 | 0 0 0 3 &intc 24 0 |
| 97 | 0 0 0 4 &intc 26 0>; |
| 98 | }; |
| 99 | |
| 100 | gpio: gpio@400d0000 { |
| 101 | compatible = "moschip,mcs814x-gpio"; |
| 102 | reg = <0x400d0000 0x670>; |
| 103 | interrupts = <10>; |
| 104 | #gpio-cells = <2>; |
| 105 | gpio-controller; |
| 106 | num-gpios = <20>; |
| 107 | }; |
| 108 | |
| 109 | eepio: gpio@400d4000 { |
| 110 | compatible = "moschip,mcs814x-gpio"; |
| 111 | reg = <0x400d4000 0x470>; |
| 112 | #gpio-cells = <2>; |
| 113 | gpio-controller; |
| 114 | num-gpios = <4>; |
| 115 | }; |
| 116 | |
| 117 | uart0: serial@400dc000 { |
| 118 | compatible = "ns16550"; |
| 119 | reg = <0x400dc000 0x20>; |
| 120 | clock-frequency = <50000000>; |
| 121 | reg-shift = <2>; |
| 122 | interrupts = <21>; |
| 123 | status = "okay"; |
| 124 | }; |
| 125 | |
| 126 | intc: interrupt-controller@400e4000 { |
| 127 | #interrupt-cells = <1>; |
| 128 | compatible = "moschip,mcs814x-intc"; |
| 129 | interrupt-controller; |
| 130 | interrupt-parent; |
| 131 | reg = <0x400e4000 0x48>; |
| 132 | }; |
| 133 | |
| 134 | m2m@400e8000 { |
| 135 | reg = <0x400e8000 0x24>; |
| 136 | interrupts = <17>; |
| 137 | }; |
| 138 | |
| 139 | eth-filters@400ec000 { |
| 140 | reg = <0x400ec000 0x80>; |
| 141 | }; |
| 142 | |
| 143 | timer: timer@400f800c { |
| 144 | compatible = "moschip,mcs814x-timer"; |
| 145 | interrupts = <0>; |
| 146 | reg = <0x400f800c 0x8>; |
| 147 | }; |
| 148 | |
| 149 | watchdog@400f8014 { |
| 150 | compatible = "moschip,mcs814x-wdt"; |
| 151 | reg = <0x400f8014 0x8>; |
| 152 | }; |
| 153 | |
| 154 | adc { |
| 155 | compatible = "simple-bus"; |
| 156 | #address-cells = <2>; |
| 157 | #size-cells = <1>; |
| 158 | // 8 64MB chip-selects |
| 159 | ranges = <0 0 0x00000000 0x4000000 // sdram |
| 160 | 1 0 0x04000000 0x4000000 // sdram |
| 161 | 2 0 0x08000000 0x4000000 // reserved |
| 162 | 3 0 0x0c000000 0x4000000 // flash/localbus |
| 163 | 4 0 0x10000000 0x4000000 // flash/localbus |
| 164 | 5 0 0x14000000 0x4000000 // flash/localbus |
| 165 | 6 0 0x18000000 0x4000000 // flash/localbus |
| 166 | 7 0 0x1c000000 0x4000000>; // flash/localbus |
| 167 | |
| 168 | sdram: memory@0,0 { |
| 169 | reg = <0 0 0>; |
| 170 | }; |
| 171 | |
| 172 | nor: flash@7,0 { |
| 173 | reg = <7 0 0x4000000>; |
| 174 | compatible = "cfi-flash"; |
| 175 | bank-width = <1>; // 8-bit external flash |
| 176 | #address-cells = <1>; |
| 177 | #size-cells = <1>; |
| 178 | }; |
| 179 | }; |
| 180 | |
| 181 | usb0: ehci@400fc000 { |
| 182 | compatible = "moschip,mcs814x-ehci", "usb-ehci"; |
| 183 | reg = <0x400fc000 0x74>; |
| 184 | interrupts = <2>; |
| 185 | }; |
| 186 | |
| 187 | usb1: ohci@400fd000 { |
| 188 | compatible = "moschip,mcs814x-ohci", "ohci-le"; |
| 189 | reg = <0x400fd000 0x74>; |
| 190 | interrupts = <11>; |
| 191 | }; |
| 192 | |
| 193 | usb2: ohci@400fe000 { |
| 194 | compatible = "moschip,mcs814x-ohci", "ohci-le"; |
| 195 | reg = <0x400fe000 0x74>; |
| 196 | interrupts = <12>; |
| 197 | }; |
| 198 | |
| 199 | usb3: otg@400ff000 { |
| 200 | compatible = "moschip,msc814x-otg", "usb-otg"; |
| 201 | reg = <0x400ff000 0x1000>; |
| 202 | interrupts = <13>; |
| 203 | }; |
| 204 | }; |
| 205 | |
| 206 | }; |
| 207 | }; |
| 208 | |
