| 1 | /* |
| 2 | * Copyright (C) 2003 Artec Design Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #ifndef __ASM_ARCH_MCS814X_H |
| 11 | #define __ASM_ARCH_MCS814X_H |
| 12 | |
| 13 | #define MCS814X_IO_BASE 0xF0000000 |
| 14 | #define MCS814X_IO_START 0x40000000 |
| 15 | #define MCS814X_IO_SIZE 0x00100000 |
| 16 | |
| 17 | /* IRQ controller register offset */ |
| 18 | #define MCS814X_IRQ_ICR 0x00 |
| 19 | #define MCS814X_IRQ_ISR 0x04 |
| 20 | #define MCS814X_IRQ_MASK 0x20 |
| 21 | #define MCS814X_IRQ_STS0 0x40 |
| 22 | |
| 23 | #define MCS814X_PHYS_BASE 0x40000000 |
| 24 | #define MCS814X_VIRT_BASE MCS814X_IO_BASE |
| 25 | |
| 26 | #define MCS814X_UART 0x000DC000 |
| 27 | #define MCS814X_DBGLED 0x000EC000 |
| 28 | #define MCS814X_SYSDBG 0x000F8000 |
| 29 | #define MCS814X_SYSDBG_SIZE 0x50 |
| 30 | |
| 31 | /* System configuration and bootstrap registers */ |
| 32 | #define SYSDBG_BS1 0x00 |
| 33 | #define CPU_FREQ_SHIFT 27 |
| 34 | #define CPU_FREQ_MASK 0x0F |
| 35 | #define SDRAM_FREQ_BIT (1 << 22) |
| 36 | |
| 37 | #define SYSDBG_BS2 0x04 |
| 38 | #define LED_CFG_MASK 0x03 |
| 39 | #define CPU_MODE_SHIFT 23 |
| 40 | #define CPU_MODE_MASK 0x03 |
| 41 | |
| 42 | #define SYSDBG_SYSCTL_MAC 0x1d |
| 43 | #define BUF_SHIFT_BIT (1 << 0) |
| 44 | |
| 45 | #define SYSDBG_SYSCTL 0x08 |
| 46 | #define SYSCTL_EMAC (1 << 0) |
| 47 | #define SYSCTL_EPHY (1 << 0) /* active low */ |
| 48 | #define SYSCTL_CIPHER (1 << 16) |
| 49 | |
| 50 | #define SYSDBG_PLL_CTL 0x3C |
| 51 | |
| 52 | #endif /* __ASM_ARCH_MCS814X_H */ |
| 53 | |
| 54 | |
