| 1 | --- a/arch/powerpc/boot/Makefile |
| 2 | +++ b/arch/powerpc/boot/Makefile |
| 3 | @@ -89,7 +89,8 @@ src-plat-$(CONFIG_44x) += treeboot-ebony |
| 4 | src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c |
| 5 | src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c |
| 6 | src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c |
| 7 | -src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c |
| 8 | +src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c \ |
| 9 | + rb600.c rb333.c |
| 10 | src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c |
| 11 | src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \ |
| 12 | cuboot-c2k.c gamecube-head.S \ |
| 13 | @@ -261,6 +262,8 @@ image-$(CONFIG_MPC834x_ITX) += cuImage. |
| 14 | image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds |
| 15 | image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds |
| 16 | image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot |
| 17 | +image-$(CONFIG_RB_PPC) += dtbImage.rb600 \ |
| 18 | + dtbImage.rb333 |
| 19 | |
| 20 | # Board ports in arch/powerpc/platform/85xx/Kconfig |
| 21 | image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads |
| 22 | --- /dev/null |
| 23 | +++ b/arch/powerpc/boot/dts/rb600.dts |
| 24 | @@ -0,0 +1,283 @@ |
| 25 | +/* |
| 26 | + * RouterBOARD 600 series Device Tree Source |
| 27 | + * |
| 28 | + * Copyright 2009 Michael Guntsche <mike@it-loops.com> |
| 29 | + * |
| 30 | + * This program is free software; you can redistribute it and/or modify it |
| 31 | + * under the terms of the GNU General Public License as published by the |
| 32 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 33 | + * option) any later version. |
| 34 | + */ |
| 35 | + |
| 36 | +/dts-v1/; |
| 37 | + |
| 38 | +/ { |
| 39 | + model = "RB600"; |
| 40 | + compatible = "MPC83xx"; |
| 41 | + #address-cells = <1>; |
| 42 | + #size-cells = <1>; |
| 43 | + |
| 44 | + aliases { |
| 45 | + ethernet0 = &enet0; |
| 46 | + ethernet1 = &enet1; |
| 47 | + pci0 = &pci0; |
| 48 | + }; |
| 49 | + |
| 50 | + chosen { |
| 51 | + bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1"; |
| 52 | + linux,stdout-path = "/soc8343@e0000000/serial@4500"; |
| 53 | + }; |
| 54 | + |
| 55 | + cpus { |
| 56 | + #address-cells = <1>; |
| 57 | + #size-cells = <0>; |
| 58 | + |
| 59 | + PowerPC,8343E@0 { |
| 60 | + device_type = "cpu"; |
| 61 | + reg = <0x0>; |
| 62 | + d-cache-line-size = <0x20>; |
| 63 | + i-cache-line-size = <0x20>; |
| 64 | + d-cache-size = <0x8000>; |
| 65 | + i-cache-size = <0x8000>; |
| 66 | + timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob |
| 67 | + clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob |
| 68 | + }; |
| 69 | + }; |
| 70 | + |
| 71 | + memory { |
| 72 | + device_type = "memory"; |
| 73 | + reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob |
| 74 | + }; |
| 75 | + |
| 76 | + cf@f9200000 { |
| 77 | + lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>; |
| 78 | + interrupt-at-level = <0x0>; |
| 79 | + interrupt-parent = <&ipic>; |
| 80 | + interrupts = <0x16 0x8>; |
| 81 | + lbc_extra_divider = <0x1>; |
| 82 | + reg = <0xf9200000 0x200000>; |
| 83 | + device_type = "rb,cf"; |
| 84 | + }; |
| 85 | + |
| 86 | + cf@f9000000 { |
| 87 | + lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>; |
| 88 | + interrupt-at-level = <0x0>; |
| 89 | + interrupt-parent = <&ipic>; |
| 90 | + interrupts = <0x14 0x8>; |
| 91 | + lbc_extra_divider = <0x1>; |
| 92 | + reg = <0xf9000000 0x200000>; |
| 93 | + device_type = "rb,cf"; |
| 94 | + }; |
| 95 | + |
| 96 | + flash { |
| 97 | + reg = <0xff800000 0x20000>; |
| 98 | + }; |
| 99 | + |
| 100 | + nnand { |
| 101 | + reg = <0xf0000000 0x1000>; |
| 102 | + }; |
| 103 | + |
| 104 | + nand { |
| 105 | + ale = <&gpio 0x6>; |
| 106 | + cle = <&gpio 0x5>; |
| 107 | + nce = <&gpio 0x4>; |
| 108 | + rdy = <&gpio 0x3>; |
| 109 | + reg = <0xf8000000 0x1000>; |
| 110 | + device_type = "rb,nand"; |
| 111 | + }; |
| 112 | + |
| 113 | + fancon { |
| 114 | + interrupt-parent = <&ipic>; |
| 115 | + interrupts = <0x17 0x8>; |
| 116 | + sense = <&gpio 0x7>; |
| 117 | + fan_on = <&gpio 0x9>; |
| 118 | + }; |
| 119 | + |
| 120 | + pci0: pci@e0008500 { |
| 121 | + device_type = "pci"; |
| 122 | + compatible = "fsl,mpc8349-pci"; |
| 123 | + reg = <0xe0008500 0x100 0xe0008300 0x8>; |
| 124 | + #address-cells = <3>; |
| 125 | + #size-cells = <2>; |
| 126 | + #interrupt-cells = <1>; |
| 127 | + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>; |
| 128 | + bus-range = <0x0 0x0>; |
| 129 | + interrupt-map = < |
| 130 | + 0x5800 0x0 0x0 0x1 &ipic 0x15 0x8 |
| 131 | + 0x6000 0x0 0x0 0x1 &ipic 0x30 0x8 |
| 132 | + 0x6000 0x0 0x0 0x2 &ipic 0x11 0x8 |
| 133 | + 0x6800 0x0 0x0 0x1 &ipic 0x11 0x8 |
| 134 | + 0x6800 0x0 0x0 0x2 &ipic 0x12 0x8 |
| 135 | + 0x7000 0x0 0x0 0x1 &ipic 0x12 0x8 |
| 136 | + 0x7000 0x0 0x0 0x2 &ipic 0x13 0x8 |
| 137 | + 0x7800 0x0 0x0 0x1 &ipic 0x13 0x8 |
| 138 | + 0x7800 0x0 0x0 0x2 &ipic 0x30 0x8 |
| 139 | + 0x8000 0x0 0x0 0x1 &ipic 0x30 0x8 |
| 140 | + 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8 |
| 141 | + 0x8000 0x0 0x0 0x3 &ipic 0x11 0x8 |
| 142 | + 0x8000 0x0 0x0 0x4 &ipic 0x13 0x8 |
| 143 | + 0xa000 0x0 0x0 0x1 &ipic 0x30 0x8 |
| 144 | + 0xa000 0x0 0x0 0x2 &ipic 0x11 0x8 |
| 145 | + 0xa000 0x0 0x0 0x3 &ipic 0x12 0x8 |
| 146 | + 0xa000 0x0 0x0 0x4 &ipic 0x13 0x8 |
| 147 | + 0xa800 0x0 0x0 0x1 &ipic 0x11 0x8 |
| 148 | + 0xa800 0x0 0x0 0x2 &ipic 0x12 0x8 |
| 149 | + 0xa800 0x0 0x0 0x3 &ipic 0x13 0x8 |
| 150 | + 0xa800 0x0 0x0 0x4 &ipic 0x30 0x8>; |
| 151 | + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 152 | + interrupt-parent = <&ipic>; |
| 153 | + }; |
| 154 | + |
| 155 | + soc8343@e0000000 { |
| 156 | + #address-cells = <1>; |
| 157 | + #size-cells = <1>; |
| 158 | + device_type = "soc"; |
| 159 | + compatible = "simple-bus"; |
| 160 | + ranges = <0x0 0xe0000000 0x100000>; |
| 161 | + reg = <0xe0000000 0x200>; |
| 162 | + bus-frequency = <0x1>; |
| 163 | + |
| 164 | + led { |
| 165 | + user_led = <0x400 0x8>; |
| 166 | + }; |
| 167 | + |
| 168 | + beeper { |
| 169 | + reg = <0x500 0x100>; |
| 170 | + }; |
| 171 | + |
| 172 | + gpio: gpio@0 { |
| 173 | + reg = <0xc08 0x4>; |
| 174 | + device-id = <0x0>; |
| 175 | + compatible = "gpio"; |
| 176 | + device_type = "gpio"; |
| 177 | + }; |
| 178 | + |
| 179 | + dma@82a8 { |
| 180 | + #address-cells = <1>; |
| 181 | + #size-cells = <1>; |
| 182 | + compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; |
| 183 | + reg = <0x82a8 4>; |
| 184 | + ranges = <0 0x8100 0x1a8>; |
| 185 | + interrupt-parent = <&ipic>; |
| 186 | + interrupts = <71 8>; |
| 187 | + cell-index = <0>; |
| 188 | + dma-channel@0 { |
| 189 | + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 190 | + reg = <0 0x80>; |
| 191 | + cell-index = <0>; |
| 192 | + interrupt-parent = <&ipic>; |
| 193 | + interrupts = <71 8>; |
| 194 | + }; |
| 195 | + dma-channel@80 { |
| 196 | + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 197 | + reg = <0x80 0x80>; |
| 198 | + cell-index = <1>; |
| 199 | + interrupt-parent = <&ipic>; |
| 200 | + interrupts = <71 8>; |
| 201 | + }; |
| 202 | + dma-channel@100 { |
| 203 | + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 204 | + reg = <0x100 0x80>; |
| 205 | + cell-index = <2>; |
| 206 | + interrupt-parent = <&ipic>; |
| 207 | + interrupts = <71 8>; |
| 208 | + }; |
| 209 | + dma-channel@180 { |
| 210 | + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 211 | + reg = <0x180 0x28>; |
| 212 | + cell-index = <3>; |
| 213 | + interrupt-parent = <&ipic>; |
| 214 | + interrupts = <71 8>; |
| 215 | + }; |
| 216 | + }; |
| 217 | + |
| 218 | + enet0: ethernet@25000 { |
| 219 | + #address-cells = <1>; |
| 220 | + #size-cells = <1>; |
| 221 | + cell-index = <0>; |
| 222 | + phy-handle = <&phy0>; |
| 223 | + tbi-handle = <&tbi0>; |
| 224 | + interrupt-parent = <&ipic>; |
| 225 | + interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>; |
| 226 | + local-mac-address = [00 00 00 00 00 00]; |
| 227 | + reg = <0x25000 0x1000>; |
| 228 | + ranges = <0x0 0x25000 0x1000>; |
| 229 | + compatible = "gianfar"; |
| 230 | + model = "TSEC"; |
| 231 | + device_type = "network"; |
| 232 | + |
| 233 | + mdio@520 { |
| 234 | + #address-cells = <1>; |
| 235 | + #size-cells = <0>; |
| 236 | + compatible = "fsl,gianfar-tbi"; |
| 237 | + reg = <0x520 0x20>; |
| 238 | + |
| 239 | + tbi0: tbi-phy@11 { |
| 240 | + reg = <0x11>; |
| 241 | + device_type = "tbi-phy"; |
| 242 | + }; |
| 243 | + }; |
| 244 | + }; |
| 245 | + |
| 246 | + enet1: ethernet@24000 { |
| 247 | + #address-cells = <1>; |
| 248 | + #size-cells = <1>; |
| 249 | + cell-index = <1>; |
| 250 | + phy-handle = <&phy1>; |
| 251 | + tbi-handle = <&tbi1>; |
| 252 | + interrupt-parent = <&ipic>; |
| 253 | + interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>; |
| 254 | + local-mac-address = [00 00 00 00 00 00]; |
| 255 | + reg = <0x24000 0x1000>; |
| 256 | + ranges = <0x0 0x24000 0x1000>; |
| 257 | + compatible = "gianfar"; |
| 258 | + model = "TSEC"; |
| 259 | + device_type = "network"; |
| 260 | + |
| 261 | + mdio@520 { |
| 262 | + #size-cells = <0x0>; |
| 263 | + #address-cells = <0x1>; |
| 264 | + reg = <0x520 0x20>; |
| 265 | + compatible = "fsl,gianfar-mdio"; |
| 266 | + |
| 267 | + phy0: ethernet-phy@0 { |
| 268 | + device_type = "ethernet-phy"; |
| 269 | + reg = <0x0>; |
| 270 | + }; |
| 271 | + |
| 272 | + phy1: ethernet-phy@1 { |
| 273 | + device_type = "ethernet-phy"; |
| 274 | + reg = <0x1>; |
| 275 | + }; |
| 276 | + |
| 277 | + tbi1: tbi-phy@11 { |
| 278 | + reg = <0x11>; |
| 279 | + device_type = "tbi-phy"; |
| 280 | + }; |
| 281 | + }; |
| 282 | + }; |
| 283 | + |
| 284 | + ipic: pic@700 { |
| 285 | + interrupt-controller; |
| 286 | + #address-cells = <0>; |
| 287 | + #interrupt-cells = <2>; |
| 288 | + reg = <0x700 0x100>; |
| 289 | + device_type = "ipic"; |
| 290 | + }; |
| 291 | + |
| 292 | + serial@4500 { |
| 293 | + interrupt-parent = <&ipic>; |
| 294 | + interrupts = <0x9 0x8>; |
| 295 | + clock-frequency = <0xfe4f840>; |
| 296 | + reg = <0x4500 0x100>; |
| 297 | + compatible = "ns16550"; |
| 298 | + device_type = "serial"; |
| 299 | + }; |
| 300 | + |
| 301 | + wdt@200 { |
| 302 | + reg = <0x200 0x100>; |
| 303 | + compatible = "mpc83xx_wdt"; |
| 304 | + device_type = "watchdog"; |
| 305 | + }; |
| 306 | + }; |
| 307 | +}; |
| 308 | --- /dev/null |
| 309 | +++ b/arch/powerpc/boot/rb600.c |
| 310 | @@ -0,0 +1,70 @@ |
| 311 | +/* |
| 312 | + * The RouterBOARD platform -- for booting RB600(A) RouterBOARDs. |
| 313 | + * |
| 314 | + * Author: Michael Guntsche <mike@it-loops.com> |
| 315 | + * |
| 316 | + * Copyright (c) 2009 Michael Guntsche |
| 317 | + * |
| 318 | + * This program is free software; you can redistribute it and/or modify it |
| 319 | + * under the terms of the GNU General Public License version 2 as published |
| 320 | + * by the Free Software Foundation. |
| 321 | + */ |
| 322 | + |
| 323 | +#include "ops.h" |
| 324 | +#include "types.h" |
| 325 | +#include "io.h" |
| 326 | +#include "stdio.h" |
| 327 | +#include <libfdt.h> |
| 328 | + |
| 329 | +BSS_STACK(4*1024); |
| 330 | + |
| 331 | +u64 memsize64; |
| 332 | +const void *fw_dtb; |
| 333 | + |
| 334 | +static void rb600_fixups(void) |
| 335 | +{ |
| 336 | + const u32 *reg, *timebase, *clock; |
| 337 | + int node, size; |
| 338 | + |
| 339 | + dt_fixup_memory(0, memsize64); |
| 340 | + |
| 341 | + /* Set the MAC addresses. */ |
| 342 | + node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@24000"); |
| 343 | + reg = fdt_getprop(fw_dtb, node, "mac-address", &size); |
| 344 | + dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg); |
| 345 | + |
| 346 | + node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@25000"); |
| 347 | + reg = fdt_getprop(fw_dtb, node, "mac-address", &size); |
| 348 | + dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg); |
| 349 | + |
| 350 | + /* Find the CPU timebase and clock frequencies. */ |
| 351 | + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu")); |
| 352 | + timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size); |
| 353 | + clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size); |
| 354 | + dt_fixup_cpu_clocks(*clock, *timebase, 0); |
| 355 | + |
| 356 | +} |
| 357 | + |
| 358 | +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, |
| 359 | + unsigned long r6, unsigned long r7) |
| 360 | +{ |
| 361 | + const u32 *reg; |
| 362 | + int node, size; |
| 363 | + |
| 364 | + fw_dtb = (const void *)r3; |
| 365 | + |
| 366 | + /* Find the memory range. */ |
| 367 | + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory")); |
| 368 | + reg = fdt_getprop(fw_dtb, node, "reg", &size); |
| 369 | + memsize64 = reg[1]; |
| 370 | + |
| 371 | + /* Now we have the memory size; initialize the heap. */ |
| 372 | + simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64); |
| 373 | + |
| 374 | + /* Prepare the device tree and find the console. */ |
| 375 | + fdt_init(_dtb_start); |
| 376 | + serial_console_init(); |
| 377 | + |
| 378 | + /* Remaining fixups... */ |
| 379 | + platform_ops.fixups = rb600_fixups; |
| 380 | +} |
| 381 | --- a/arch/powerpc/boot/wrapper |
| 382 | +++ b/arch/powerpc/boot/wrapper |
| 383 | @@ -217,7 +217,7 @@ ps3) |
| 384 | make_space=n |
| 385 | pie= |
| 386 | ;; |
| 387 | -ep88xc|ep405|ep8248e) |
| 388 | +ep88xc|ep405|ep8248e|rb600|rb333) |
| 389 | platformo="$object/fixed-head.o $object/$platform.o" |
| 390 | binary=y |
| 391 | ;; |
| 392 | --- a/arch/powerpc/platforms/83xx/Kconfig |
| 393 | +++ b/arch/powerpc/platforms/83xx/Kconfig |
| 394 | @@ -38,6 +38,15 @@ config MPC832x_RDB |
| 395 | help |
| 396 | This option enables support for the MPC8323 RDB board. |
| 397 | |
| 398 | +config RB_PPC |
| 399 | + bool "MikroTik RouterBOARD 333/600 series" |
| 400 | + select DEFAULT_UIMAGE |
| 401 | + select QUICC_ENGINE |
| 402 | + select PPC_MPC832x |
| 403 | + select PPC_MPC834x |
| 404 | + help |
| 405 | + This option enables support for MikroTik RouterBOARD 333/600 series boards. |
| 406 | + |
| 407 | config MPC834x_MDS |
| 408 | bool "Freescale MPC834x MDS" |
| 409 | select DEFAULT_UIMAGE |
| 410 | --- /dev/null |
| 411 | +++ b/arch/powerpc/boot/dts/rb333.dts |
| 412 | @@ -0,0 +1,426 @@ |
| 413 | + |
| 414 | +/* |
| 415 | + * RouterBOARD 333 series Device Tree Source |
| 416 | + * |
| 417 | + * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com> |
| 418 | + * Copyright 2009 Michael Guntsche <mike@it-loops.com> |
| 419 | + * |
| 420 | + * This program is free software; you can redistribute it and/or modify it |
| 421 | + * under the terms of the GNU General Public License as published by the |
| 422 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 423 | + * option) any later version. |
| 424 | + * |
| 425 | + * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) |
| 426 | + * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1) |
| 427 | + * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0 |
| 428 | + * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0 |
| 429 | + * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property |
| 430 | + * |
| 431 | + */ |
| 432 | + |
| 433 | + |
| 434 | +/dts-v1/; |
| 435 | + |
| 436 | +/ { |
| 437 | + model = "RB333"; |
| 438 | + compatible = "MPC83xx"; |
| 439 | + #size-cells = <1>; |
| 440 | + #address-cells = <1>; |
| 441 | + |
| 442 | + aliases { |
| 443 | + ethernet0 = &enet0; |
| 444 | + ethernet1 = &enet1; |
| 445 | + ethernet2 = &enet2; |
| 446 | + pci0 = &pci0; |
| 447 | + }; |
| 448 | + |
| 449 | + chosen { |
| 450 | + bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1"; |
| 451 | + // linux,platform = <0x8062>; |
| 452 | + // linux,initrd = <0x488000 0x0>; |
| 453 | + linux,stdout-path = "/soc8323@e0000000/serial@4500"; |
| 454 | + // interrupt-controller = <&ipic>; |
| 455 | + }; |
| 456 | + |
| 457 | + cpus { |
| 458 | + #cpus = <1>; |
| 459 | + #size-cells = <0>; |
| 460 | + #address-cells = <1>; |
| 461 | + |
| 462 | + PowerPC,8323E@0 { |
| 463 | + device_type = "cpu"; |
| 464 | + reg = <0x0>; |
| 465 | + i-cache-size = <0x4000>; |
| 466 | + d-cache-size = <0x4000>; |
| 467 | + i-cache-line-size = <0x20>; |
| 468 | + d-cache-line-size = <0x20>; |
| 469 | + // clock-frequency = <0x13de3650>; |
| 470 | + // timebase-frequency = <0x1fc9f08>; |
| 471 | + timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob |
| 472 | + clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob |
| 473 | + 32-bit; |
| 474 | + }; |
| 475 | + }; |
| 476 | + |
| 477 | + memory { |
| 478 | + device_type = "memory"; |
| 479 | + reg = <0x0 0x4000000>; |
| 480 | + // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob |
| 481 | + }; |
| 482 | + |
| 483 | + flash { |
| 484 | + reg = <0xfe000000 0x20000>; |
| 485 | + }; |
| 486 | + |
| 487 | + nand { |
| 488 | + ale = <&gpio2 0x3>; |
| 489 | + cle = <&gpio2 0x2>; |
| 490 | + nce = <&gpio2 0x1>; |
| 491 | + rdy = <&gpio2 0x0>; |
| 492 | + reg = <0xf8000000 0x1000>; |
| 493 | + device_type = "rb,nand"; |
| 494 | + }; |
| 495 | + |
| 496 | + nnand { |
| 497 | + reg = <0xf0000000 0x1000>; |
| 498 | + }; |
| 499 | + |
| 500 | + voltage { |
| 501 | + voltage_gpio = <&gpio3 0x11>; |
| 502 | + }; |
| 503 | + |
| 504 | + fancon { |
| 505 | + interrupt-parent = <&ipic>; |
| 506 | + interrupts = <0x14 0x8>; |
| 507 | + fan_on = <&gpio0 0x10>; |
| 508 | + }; |
| 509 | + |
| 510 | + soc8323@e0000000 { |
| 511 | + #address-cells = <1>; |
| 512 | + #size-cells = <1>; |
| 513 | + device_type = "soc"; |
| 514 | + compatible = "simple-bus"; |
| 515 | + ranges = <0x0 0xe0000000 0x00100000>; |
| 516 | + reg = <0xe0000000 0x00000200>; |
| 517 | + bus-frequency = <1>; |
| 518 | + |
| 519 | + wdt@200 { |
| 520 | + device_type = "watchdog"; |
| 521 | + compatible = "mpc83xx_wdt"; |
| 522 | + reg = <0x200 0x100>; |
| 523 | + }; |
| 524 | + |
| 525 | + ipic:pic@700 { |
| 526 | + interrupt-controller; |
| 527 | + #address-cells = <0>; |
| 528 | + #interrupt-cells = <2>; |
| 529 | + reg = <0x700 0x100>; |
| 530 | + device_type = "ipic"; |
| 531 | + }; |
| 532 | + |
| 533 | + par_io@1400 { |
| 534 | + num-ports = <4>; |
| 535 | + device_type = "par_io"; |
| 536 | + reg = <0x1400 0x100>; |
| 537 | + |
| 538 | + ucc2pio: ucc_pin@02 { |
| 539 | + pio-map = < |
| 540 | + /* port pin dir open_drain assignment has_irq */ |
| 541 | + 3 4 3 0 2 0 |
| 542 | + 3 5 1 0 2 0 |
| 543 | + 0 18 1 0 1 0 |
| 544 | + 0 19 1 0 1 0 |
| 545 | + 0 20 1 0 1 0 |
| 546 | + 0 21 1 0 1 0 |
| 547 | + 0 30 1 0 1 0 |
| 548 | + 3 6 2 0 1 0 |
| 549 | + 0 29 2 0 1 0 |
| 550 | + 0 31 2 0 1 0 |
| 551 | + 0 22 2 0 1 0 |
| 552 | + 0 23 2 0 1 0 |
| 553 | + 0 24 2 0 1 0 |
| 554 | + 0 25 2 0 1 0 |
| 555 | + 0 28 2 0 1 0 |
| 556 | + 0 26 2 0 1 0 |
| 557 | + 3 31 2 0 1 0>; |
| 558 | + }; |
| 559 | + |
| 560 | + ucc3pio: ucc_pin@03 { |
| 561 | + pio-map = < |
| 562 | + /* port pin dir open_drain assignment has_irq */ |
| 563 | + 1 0 1 0 1 0 |
| 564 | + 1 1 1 0 1 0 |
| 565 | + 1 2 1 0 1 0 |
| 566 | + 1 3 1 0 1 0 |
| 567 | + 1 12 1 0 1 0 |
| 568 | + 3 24 2 0 1 0 |
| 569 | + 1 11 2 0 1 0 |
| 570 | + 1 13 2 0 1 0 |
| 571 | + 1 4 2 0 1 0 |
| 572 | + 1 5 2 0 1 0 |
| 573 | + 1 6 2 0 1 0 |
| 574 | + 1 7 2 0 1 0 |
| 575 | + 1 10 2 0 1 0 |
| 576 | + 1 8 2 0 1 0 |
| 577 | + 3 29 2 0 1 0>; |
| 578 | + }; |
| 579 | + |
| 580 | + ucc4pio: ucc_pin@04 { |
| 581 | + pio-map = < |
| 582 | + /* port pin dir open_drain assignment has_irq */ |
| 583 | + 1 18 1 0 1 0 |
| 584 | + 1 19 1 0 1 0 |
| 585 | + 1 20 1 0 1 0 |
| 586 | + 1 21 1 0 1 0 |
| 587 | + 1 30 1 0 1 0 |
| 588 | + 3 20 2 0 1 0 |
| 589 | + 1 30 2 0 1 0 |
| 590 | + 1 31 2 0 1 0 |
| 591 | + 1 22 2 0 1 0 |
| 592 | + 1 23 2 0 1 0 |
| 593 | + 1 24 2 0 1 0 |
| 594 | + 1 25 2 0 1 0 |
| 595 | + 1 28 2 0 1 0 |
| 596 | + 1 26 2 0 1 0 |
| 597 | + 3 21 2 0 1 0>; |
| 598 | + }; |
| 599 | + }; |
| 600 | + |
| 601 | + serial0: serial@4500 { |
| 602 | + cell-index = <0>; |
| 603 | + device_type = "serial"; |
| 604 | + compatible = "fsl,ns16550", "ns16550"; |
| 605 | + reg = <0x4500 0x100>; |
| 606 | + clock-frequency = <0x7f27c20>; |
| 607 | + interrupts = <9 0x8>; |
| 608 | + interrupt-parent = <&ipic>; |
| 609 | + }; |
| 610 | + |
| 611 | + dma@82a8 { |
| 612 | + #address-cells = <1>; |
| 613 | + #size-cells = <1>; |
| 614 | + compatible = "fsl,mpc8323-dma", "fsl,elo-dma"; |
| 615 | + reg = <0x82a8 4>; |
| 616 | + ranges = <0 0x8100 0x1a8>; |
| 617 | + interrupt-parent = <&ipic>; |
| 618 | + interrupts = <71 8>; |
| 619 | + cell-index = <0>; |
| 620 | + dma-channel@0 { |
| 621 | + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; |
| 622 | + reg = <0 0x80>; |
| 623 | + cell-index = <0>; |
| 624 | + interrupt-parent = <&ipic>; |
| 625 | + interrupts = <71 8>; |
| 626 | + }; |
| 627 | + dma-channel@80 { |
| 628 | + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; |
| 629 | + reg = <0x80 0x80>; |
| 630 | + cell-index = <1>; |
| 631 | + interrupt-parent = <&ipic>; |
| 632 | + interrupts = <71 8>; |
| 633 | + }; |
| 634 | + dma-channel@100 { |
| 635 | + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; |
| 636 | + reg = <0x100 0x80>; |
| 637 | + cell-index = <2>; |
| 638 | + interrupt-parent = <&ipic>; |
| 639 | + interrupts = <71 8>; |
| 640 | + }; |
| 641 | + dma-channel@180 { |
| 642 | + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; |
| 643 | + reg = <0x180 0x28>; |
| 644 | + cell-index = <3>; |
| 645 | + interrupt-parent = <&ipic>; |
| 646 | + interrupts = <71 8>; |
| 647 | + }; |
| 648 | + }; |
| 649 | + |
| 650 | + beeper { |
| 651 | + gpio = <&gpio3 0x12>; |
| 652 | + reg = <0x500 0x100>; |
| 653 | + interrupt-parent = <&ipic>; |
| 654 | + interrupts = <0x48 0x8>; |
| 655 | + }; |
| 656 | + |
| 657 | + gpio3: gpio@3 { |
| 658 | + reg = <0x144c 0x4>; |
| 659 | + device-id = <0x3>; |
| 660 | + compatible = "qe_gpio"; |
| 661 | + device_type = "gpio"; |
| 662 | + }; |
| 663 | + |
| 664 | + gpio2: gpio@2 { |
| 665 | + reg = <0x1434 0x4>; |
| 666 | + device-id = <0x2>; |
| 667 | + compatible = "qe_gpio"; |
| 668 | + device_type = "gpio"; |
| 669 | + }; |
| 670 | + |
| 671 | + gpio0: gpio@0 { |
| 672 | + reg = <0x1404 0x4>; |
| 673 | + device-id = <0x0>; |
| 674 | + compatible = "qe_gpio"; |
| 675 | + device_type = "gpio"; |
| 676 | + }; |
| 677 | + }; |
| 678 | + |
| 679 | + pci0: pci@e0008500 { |
| 680 | + device_type = "pci"; |
| 681 | + // compatible = "83xx"; |
| 682 | + compatible = "fsl,mpc8349-pci"; |
| 683 | + reg = <0xe0008500 0x100 0xe0008300 0x8>; |
| 684 | + #address-cells = <3>; |
| 685 | + #size-cells = <2>; |
| 686 | + #interrupt-cells = <1>; |
| 687 | + // clock-frequency = <0>; |
| 688 | + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>; |
| 689 | + bus-range = <0x0 0x0>; |
| 690 | + interrupt-map = < |
| 691 | + /* IDSEL 0x10 AD16 miniPCI slot 0 */ |
| 692 | + 0x8000 0x0 0x0 0x1 &ipic 0x11 0x8 |
| 693 | + 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8 |
| 694 | + |
| 695 | + /* IDSEL 0x11 AD17 miniPCI slot 1 */ |
| 696 | + 0x8800 0x0 0x0 0x1 &ipic 0x12 0x8 |
| 697 | + 0x8800 0x0 0x0 0x2 &ipic 0x13 0x8 |
| 698 | + |
| 699 | + /* IDSEL 0x12 AD18 miniPCI slot 2 */ |
| 700 | + 0x9000 0x0 0x0 0x1 &ipic 0x13 0x8 |
| 701 | + 0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>; |
| 702 | + |
| 703 | + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 704 | + interrupt-parent = <&ipic>; |
| 705 | + // interrupts = <66 0x8>; |
| 706 | + }; |
| 707 | + |
| 708 | + qe@e0100000 { |
| 709 | + reg = <0xe0100000 0x480>; |
| 710 | + ranges = <0x0 0xe0100000 0x100000>; |
| 711 | + model = "QE"; |
| 712 | + device_type = "qe"; |
| 713 | + compatible = "fsl,qe"; |
| 714 | + #size-cells = <1>; |
| 715 | + #address-cells = <1>; |
| 716 | + brg-frequency = <0>; |
| 717 | + bus-frequency = <0>; |
| 718 | + // bus-frequency = <198000000>; |
| 719 | + fsl,qe-num-riscs = <1>; |
| 720 | + fsl,qe-num-snums = <28>; |
| 721 | + |
| 722 | + qeic: qeic@80 { |
| 723 | + interrupt-controller; |
| 724 | + compatible = "fsl,qe-ic"; |
| 725 | + big-endian; |
| 726 | + built-in; |
| 727 | + reg = <0x80 0x80>; |
| 728 | + #interrupt-cells = <1>; |
| 729 | + #address-cells = <0>; |
| 730 | + device_type = "qeic"; |
| 731 | + interrupts = <0x20 0x8 0x21 0x8>; |
| 732 | + interrupt-parent = <&ipic>; |
| 733 | + }; |
| 734 | + |
| 735 | + mdio@2120 { |
| 736 | + compatible = "ucc_geth_phy"; |
| 737 | + device_type = "mdio"; |
| 738 | + reg = <0x3120 0x18>; |
| 739 | + #size-cells = <0>; |
| 740 | + #address-cells = <1>; |
| 741 | + |
| 742 | + phy3: ethernet-phy@03 { |
| 743 | + // interface = <0x3>; |
| 744 | + device_type = "ethernet-phy"; |
| 745 | + reg = <0x3>; |
| 746 | + }; |
| 747 | + |
| 748 | + phy2: ethernet-phy@02 { |
| 749 | + // interface = <0x3>; |
| 750 | + device_type = "ethernet-phy"; |
| 751 | + reg = <0x2>; |
| 752 | + }; |
| 753 | + |
| 754 | + phy1: ethernet-phy@01 { |
| 755 | + // interface = <0x3>; |
| 756 | + device_type = "ethernet-phy"; |
| 757 | + reg = <0x1>; |
| 758 | + }; |
| 759 | + }; |
| 760 | + |
| 761 | + enet0: ucc@2200 { |
| 762 | + tx-clock = <0x1a>; |
| 763 | + rx-clock = <0x1f>; |
| 764 | + local-mac-address = [00 00 00 00 00 00]; |
| 765 | + interrupt-parent = <&qeic>; |
| 766 | + interrupts = <0x22>; |
| 767 | + reg = <0x2200 0x200>; |
| 768 | + device-id = <0x3>; |
| 769 | + model = "UCC"; |
| 770 | + compatible = "ucc_geth"; |
| 771 | + device_type = "network"; |
| 772 | + phy-handle = <&phy2>; |
| 773 | + pio-handle = <&ucc3pio>; |
| 774 | + }; |
| 775 | + |
| 776 | + enet1: ucc@3200 { |
| 777 | + tx-clock = <0x22>; |
| 778 | + rx-clock = <0x20>; |
| 779 | + local-mac-address = [00 00 00 00 00 00]; |
| 780 | + interrupt-parent = <&qeic>; |
| 781 | + interrupts = <0x23>; |
| 782 | + reg = <0x3200 0x200>; |
| 783 | + device-id = <0x4>; |
| 784 | + model = "UCC"; |
| 785 | + compatible = "ucc_geth"; |
| 786 | + device_type = "network"; |
| 787 | + phy-handle = <&phy3>; |
| 788 | + pio-handle = <&ucc4pio>; |
| 789 | + }; |
| 790 | + |
| 791 | + enet2: ucc@3000 { |
| 792 | + tx-clock = <0x18>; |
| 793 | + rx-clock = <0x17>; |
| 794 | + local-mac-address = [00 00 00 00 00 00]; |
| 795 | + interrupt-parent = <&qeic>; |
| 796 | + interrupts = <0x21>; |
| 797 | + reg = <0x3000 0x200>; |
| 798 | + device-id = <0x2>; |
| 799 | + model = "UCC"; |
| 800 | + compatible = "ucc_geth"; |
| 801 | + device_type = "network"; |
| 802 | + phy-handle = <&phy1>; |
| 803 | + pio-handle = <&ucc2pio>; |
| 804 | + }; |
| 805 | + |
| 806 | + spi@500 { |
| 807 | + mode = "cpu"; |
| 808 | + interrupt-parent = <&qeic>; |
| 809 | + interrupts = <0x1>; |
| 810 | + reg = <0x500 0x40>; |
| 811 | + compatible = "fsl,spi"; |
| 812 | + device_type = "spi"; |
| 813 | + }; |
| 814 | + |
| 815 | + spi@4c0 { |
| 816 | + mode = "cpu"; |
| 817 | + interrupt-parent = <&qeic>; |
| 818 | + interrupts = <0x2>; |
| 819 | + reg = <0x4c0 0x40>; |
| 820 | + compatible = "fsl,spi"; |
| 821 | + device_type = "spi"; |
| 822 | + }; |
| 823 | + |
| 824 | + muram@10000 { |
| 825 | + #address-cells = <1>; |
| 826 | + #size-cells = <1>; |
| 827 | + compatible = "fsl,qe-muram", "fsl,cpm-muram"; |
| 828 | + ranges = <0x0 0x10000 0x4000>; |
| 829 | + device_type = "muram"; |
| 830 | + |
| 831 | + data-only@0 { |
| 832 | + compatible = "fsl,qe-muram-data", |
| 833 | + "fsl,cpm-muram-data"; |
| 834 | + reg = <0x0 0x4000>; |
| 835 | + }; |
| 836 | + }; |
| 837 | + }; |
| 838 | +}; |
| 839 | --- /dev/null |
| 840 | +++ b/arch/powerpc/boot/rb333.c |
| 841 | @@ -0,0 +1,86 @@ |
| 842 | +/* |
| 843 | + * The RouterBOARD platform -- for booting RB333 RouterBOARDs. |
| 844 | + * |
| 845 | + * Author: Alexandros C. Couloumbis <alex@ozo.com> |
| 846 | + * Author: Michael Guntsche <mike@it-loops.com> |
| 847 | + * |
| 848 | + * Copyright (c) 2010 Alexandros C. Couloumbis |
| 849 | + * Copyright (c) 2009 Michael Guntsche |
| 850 | + * |
| 851 | + * This program is free software; you can redistribute it and/or modify it |
| 852 | + * under the terms of the GNU General Public License version 2 as published |
| 853 | + * by the Free Software Foundation. |
| 854 | + */ |
| 855 | + |
| 856 | +#include "ops.h" |
| 857 | +#include "types.h" |
| 858 | +#include "io.h" |
| 859 | +#include "stdio.h" |
| 860 | +#include <libfdt.h> |
| 861 | + |
| 862 | +BSS_STACK(4*1024); |
| 863 | + |
| 864 | +u64 memsize64; |
| 865 | +const void *fw_dtb; |
| 866 | + |
| 867 | +static void rb333_fixups(void) |
| 868 | +{ |
| 869 | + const u32 *reg, *timebase, *clock; |
| 870 | + int node, size; |
| 871 | + void *chosen; |
| 872 | + const char* bootargs; |
| 873 | + |
| 874 | + dt_fixup_memory(0, memsize64); |
| 875 | + |
| 876 | + /* Find the CPU timebase and clock frequencies. */ |
| 877 | + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu")); |
| 878 | + timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size); |
| 879 | + clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size); |
| 880 | + dt_fixup_cpu_clocks(*clock, *timebase, 0); |
| 881 | + |
| 882 | + /* Set the MAC addresses. */ |
| 883 | + node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@2200"); |
| 884 | + reg = fdt_getprop(fw_dtb, node, "mac-address", &size); |
| 885 | + dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg); |
| 886 | + |
| 887 | + node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@3200"); |
| 888 | + reg = fdt_getprop(fw_dtb, node, "mac-address", &size); |
| 889 | + dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg); |
| 890 | + |
| 891 | + node = fdt_path_offset(fw_dtb, "/qe@e0100000/ucc@3000"); |
| 892 | + reg = fdt_getprop(fw_dtb, node, "mac-address", &size); |
| 893 | + dt_fixup_mac_address_by_alias("ethernet2", (const u8 *)reg); |
| 894 | + |
| 895 | + /* Fixup chosen |
| 896 | + * The bootloader reads the kernelparm segment and adds the content to |
| 897 | + * bootargs. This is needed to specify root and other boot flags. |
| 898 | + */ |
| 899 | + chosen = finddevice("/chosen"); |
| 900 | + node = fdt_path_offset(fw_dtb, "/chosen"); |
| 901 | + bootargs = fdt_getprop(fw_dtb, node, "bootargs", &size); |
| 902 | + setprop_str(chosen, "bootargs", bootargs); |
| 903 | +} |
| 904 | + |
| 905 | +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, |
| 906 | + unsigned long r6, unsigned long r7) |
| 907 | +{ |
| 908 | + const u32 *reg; |
| 909 | + int node, size; |
| 910 | + |
| 911 | + fw_dtb = (const void *)r3; |
| 912 | + |
| 913 | + /* Find the memory range. */ |
| 914 | + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory")); |
| 915 | + reg = fdt_getprop(fw_dtb, node, "reg", &size); |
| 916 | + memsize64 = reg[1]; |
| 917 | + |
| 918 | + /* Now we have the memory size; initialize the heap. */ |
| 919 | + simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64); |
| 920 | + |
| 921 | + /* Prepare the device tree and find the console. */ |
| 922 | + fdt_init(_dtb_start); |
| 923 | + serial_console_init(); |
| 924 | + |
| 925 | + /* Remaining fixups... */ |
| 926 | + platform_ops.fixups = rb333_fixups; |
| 927 | +} |
| 928 | --- /dev/null |
| 929 | +++ b/arch/powerpc/platforms/83xx/rbppc.c |
| 930 | @@ -0,0 +1,388 @@ |
| 931 | +/* |
| 932 | + * Copyright (C) 2010 Alexandros C. Couloumbis <alex@ozo.com> |
| 933 | + * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org> |
| 934 | + * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com> |
| 935 | + * Copyright (C) Mikrotik 2007 |
| 936 | + * |
| 937 | + * This program is free software; you can redistribute it and/or modify it |
| 938 | + * under the terms of the GNU General Public License as published by the |
| 939 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 940 | + * option) any later version. |
| 941 | + */ |
| 942 | + |
| 943 | +#include <linux/delay.h> |
| 944 | +#include <linux/root_dev.h> |
| 945 | +#include <linux/initrd.h> |
| 946 | +#include <linux/interrupt.h> |
| 947 | +#include <linux/of_platform.h> |
| 948 | +#include <linux/of_device.h> |
| 949 | +#include <linux/of_platform.h> |
| 950 | +#include <linux/pci.h> |
| 951 | +#include <asm/time.h> |
| 952 | +#include <asm/ipic.h> |
| 953 | +#include <asm/udbg.h> |
| 954 | +#include <asm/qe.h> |
| 955 | +#include <asm/qe_ic.h> |
| 956 | +#include <sysdev/fsl_soc.h> |
| 957 | +#include <sysdev/fsl_pci.h> |
| 958 | +#include "mpc83xx.h" |
| 959 | + |
| 960 | +#define SYSCTL 0x100 |
| 961 | +#define SICRL 0x014 |
| 962 | + |
| 963 | +#define GTCFR2 0x04 |
| 964 | +#define GTMDR4 0x22 |
| 965 | +#define GTRFR4 0x26 |
| 966 | +#define GTCNR4 0x2e |
| 967 | +#define GTVER4 0x36 |
| 968 | +#define GTPSR4 0x3e |
| 969 | + |
| 970 | +#define GTCFR_BCM 0x40 |
| 971 | +#define GTCFR_STP4 0x20 |
| 972 | +#define GTCFR_RST4 0x10 |
| 973 | +#define GTCFR_STP3 0x02 |
| 974 | +#define GTCFR_RST3 0x01 |
| 975 | + |
| 976 | +#define GTMDR_ORI 0x10 |
| 977 | +#define GTMDR_FRR 0x08 |
| 978 | +#define GTMDR_ICLK16 0x04 |
| 979 | + |
| 980 | +extern int par_io_data_set(u8 port, u8 pin, u8 val); |
| 981 | +extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, |
| 982 | + int assignment, int has_irq); |
| 983 | + |
| 984 | +static unsigned timer_freq; |
| 985 | +static void *gtm; |
| 986 | + |
| 987 | +static int beeper_irq; |
| 988 | +static unsigned beeper_gpio_pin[2]; |
| 989 | + |
| 990 | +int rb333model = 0; |
| 991 | + |
| 992 | +irqreturn_t rbppc_timer_irq(int irq, void *ptr) |
| 993 | +{ |
| 994 | + static int toggle = 0; |
| 995 | + |
| 996 | + par_io_data_set(beeper_gpio_pin[0], beeper_gpio_pin[1], toggle); |
| 997 | + toggle = !toggle; |
| 998 | + |
| 999 | + /* ack interrupt */ |
| 1000 | + out_be16(gtm + GTVER4, 3); |
| 1001 | + |
| 1002 | + return IRQ_HANDLED; |
| 1003 | +} |
| 1004 | + |
| 1005 | +void rbppc_beep(unsigned freq) |
| 1006 | +{ |
| 1007 | + unsigned gtmdr; |
| 1008 | + |
| 1009 | + if (freq > 5000) freq = 5000; |
| 1010 | + |
| 1011 | + if (!gtm) |
| 1012 | + return; |
| 1013 | + if (!freq) { |
| 1014 | + out_8(gtm + GTCFR2, GTCFR_STP4 | GTCFR_STP3); |
| 1015 | + return; |
| 1016 | + } |
| 1017 | + |
| 1018 | + out_8(gtm + GTCFR2, GTCFR_RST4 | GTCFR_STP3); |
| 1019 | + out_be16(gtm + GTPSR4, 255); |
| 1020 | + gtmdr = GTMDR_FRR | GTMDR_ICLK16; |
| 1021 | + if (beeper_irq != NO_IRQ) gtmdr |= GTMDR_ORI; |
| 1022 | + out_be16(gtm + GTMDR4, gtmdr); |
| 1023 | + out_be16(gtm + GTVER4, 3); |
| 1024 | + |
| 1025 | + out_be16(gtm + GTRFR4, timer_freq / 16 / 256 / freq / 2); |
| 1026 | + out_be16(gtm + GTCNR4, 0); |
| 1027 | +} |
| 1028 | +EXPORT_SYMBOL(rbppc_beep); |
| 1029 | + |
| 1030 | +static void __init rbppc_setup_arch(void) |
| 1031 | +{ |
| 1032 | + struct device_node *np; |
| 1033 | + |
| 1034 | + np = of_find_node_by_type(NULL, "cpu"); |
| 1035 | + if (np) { |
| 1036 | + const unsigned *fp = of_get_property(np, "clock-frequency", NULL); |
| 1037 | + loops_per_jiffy = fp ? *fp / HZ : 0; |
| 1038 | + |
| 1039 | + of_node_put(np); |
| 1040 | + } |
| 1041 | + |
| 1042 | + np = of_find_node_by_name(NULL, "serial"); |
| 1043 | + if (np) { |
| 1044 | + timer_freq = |
| 1045 | + *(unsigned *) of_get_property(np, "clock-frequency", NULL); |
| 1046 | + of_node_put(np); |
| 1047 | + } |
| 1048 | + |
| 1049 | +#ifdef CONFIG_PCI |
| 1050 | + np = of_find_node_by_type(NULL, "pci"); |
| 1051 | + if (np) { |
| 1052 | + mpc83xx_add_bridge(np); |
| 1053 | + } |
| 1054 | +#endif |
| 1055 | + |
| 1056 | +if (rb333model) { |
| 1057 | + |
| 1058 | +#ifdef CONFIG_QUICC_ENGINE |
| 1059 | + qe_reset(); |
| 1060 | + |
| 1061 | + if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { |
| 1062 | + par_io_init(np); |
| 1063 | + of_node_put(np); |
| 1064 | + |
| 1065 | + for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) |
| 1066 | + par_io_of_config(np); |
| 1067 | + } |
| 1068 | +#endif |
| 1069 | + |
| 1070 | +} /* RB333 */ |
| 1071 | + |
| 1072 | +} |
| 1073 | + |
| 1074 | +void __init rbppc_init_IRQ(void) |
| 1075 | +{ |
| 1076 | + struct device_node *np; |
| 1077 | + |
| 1078 | + np = of_find_node_by_type(NULL, "ipic"); |
| 1079 | + if (np) { |
| 1080 | + ipic_init(np, 0); |
| 1081 | + ipic_set_default_priority(); |
| 1082 | + of_node_put(np); |
| 1083 | + } |
| 1084 | + |
| 1085 | +if (rb333model) { |
| 1086 | + |
| 1087 | +#ifdef CONFIG_QUICC_ENGINE |
| 1088 | + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); |
| 1089 | + if (!np) { |
| 1090 | + np = of_find_node_by_type(NULL, "qeic"); |
| 1091 | + if (!np) |
| 1092 | + return; |
| 1093 | + } |
| 1094 | + qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic); |
| 1095 | + of_node_put(np); |
| 1096 | +#endif /* CONFIG_QUICC_ENGINE */ |
| 1097 | + |
| 1098 | +} /* RB333 */ |
| 1099 | + |
| 1100 | +} |
| 1101 | + |
| 1102 | +static int __init rbppc_probe(void) |
| 1103 | +{ |
| 1104 | + char *model; |
| 1105 | + |
| 1106 | + model = of_get_flat_dt_prop(of_get_flat_dt_root(), "model", NULL); |
| 1107 | + |
| 1108 | + if (!model) |
| 1109 | + return 0; |
| 1110 | + |
| 1111 | + if (strcmp(model, "RB333") == 0) { |
| 1112 | + rb333model = 1; |
| 1113 | + return 1; |
| 1114 | + } |
| 1115 | + |
| 1116 | + if (strcmp(model, "RB600") == 0) |
| 1117 | + return 1; |
| 1118 | + |
| 1119 | + return 0; |
| 1120 | +} |
| 1121 | + |
| 1122 | +static void __init rbppc_beeper_init(struct device_node *beeper) |
| 1123 | +{ |
| 1124 | + struct resource res; |
| 1125 | + struct device_node *gpio; |
| 1126 | + const unsigned *pin; |
| 1127 | + const unsigned *gpio_id; |
| 1128 | + |
| 1129 | + if (of_address_to_resource(beeper, 0, &res)) { |
| 1130 | + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No region specified\n", beeper->full_name); |
| 1131 | + return; |
| 1132 | + } |
| 1133 | + |
| 1134 | + pin = of_get_property(beeper, "gpio", NULL); |
| 1135 | + if (pin) { |
| 1136 | + gpio = of_find_node_by_phandle(pin[0]); |
| 1137 | + |
| 1138 | + if (!gpio) { |
| 1139 | + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: GPIO handle %x not found\n", beeper->full_name, pin[0]); |
| 1140 | + return; |
| 1141 | + } |
| 1142 | + |
| 1143 | + gpio_id = of_get_property(gpio, "device-id", NULL); |
| 1144 | + if (!gpio_id) { |
| 1145 | + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No device-id specified in GPIO\n", beeper->full_name); |
| 1146 | + return; |
| 1147 | + } |
| 1148 | + |
| 1149 | + beeper_gpio_pin[0] = *gpio_id; |
| 1150 | + beeper_gpio_pin[1] = pin[1]; |
| 1151 | + |
| 1152 | + par_io_config_pin(*gpio_id, pin[1], 1, 0, 0, 0); |
| 1153 | + } else { |
| 1154 | + void *sysctl; |
| 1155 | + |
| 1156 | + sysctl = ioremap_nocache(get_immrbase() + SYSCTL, 0x100); |
| 1157 | + out_be32(sysctl + SICRL, |
| 1158 | + in_be32(sysctl + SICRL) | (1 << (31 - 19))); |
| 1159 | + iounmap(sysctl); |
| 1160 | + } |
| 1161 | + |
| 1162 | + gtm = ioremap_nocache(res.start, res.end - res.start + 1); |
| 1163 | + |
| 1164 | + beeper_irq = irq_of_parse_and_map(beeper, 0); |
| 1165 | + if (beeper_irq != NO_IRQ) { |
| 1166 | + int e = request_irq(beeper_irq, rbppc_timer_irq, 0, "beeper", NULL); |
| 1167 | + if (e) { |
| 1168 | + printk(KERN_ERR "rbppc_beeper_init(%s): Request of beeper irq failed!\n", beeper->full_name); |
| 1169 | + } |
| 1170 | + } |
| 1171 | +} |
| 1172 | + |
| 1173 | +#define SBIT(x) (0x80000000 >> (x)) |
| 1174 | +#define DBIT(x, y) ((y) << (32 - (((x % 16) + 1) * 2))) |
| 1175 | + |
| 1176 | +#define GPIO_DIR_RB333(x) ((x) + (0x1408 >> 2)) |
| 1177 | +#define GPIO_DATA_RB333(x) ((x) + (0x1404 >> 2)) |
| 1178 | + |
| 1179 | +#define SICRL_RB600(x) ((x) + (0x114 >> 2)) |
| 1180 | +#define GPIO_DIR_RB600(x) ((x) + (0xc00 >> 2)) |
| 1181 | +#define GPIO_DATA_RB600(x) ((x) + (0xc08 >> 2)) |
| 1182 | + |
| 1183 | +static void rbppc_restart(char *cmd) |
| 1184 | +{ |
| 1185 | + __be32 __iomem *reg; |
| 1186 | + unsigned rb_model; |
| 1187 | + struct device_node *root; |
| 1188 | + unsigned int size; |
| 1189 | + |
| 1190 | + root = of_find_node_by_path("/"); |
| 1191 | + if (root) { |
| 1192 | + const char *prop = (char *) of_get_property(root, "model", &size); |
| 1193 | + rb_model = prop[sizeof("RB") - 1] - '0'; |
| 1194 | + of_node_put(root); |
| 1195 | + switch (rb_model) { |
| 1196 | + case 3: |
| 1197 | + reg = ioremap(get_immrbase(), 0x2000); |
| 1198 | + local_irq_disable(); |
| 1199 | + out_be32(GPIO_DIR_RB333(reg), |
| 1200 | + (in_be32(GPIO_DIR_RB333(reg)) & ~DBIT(4, 3)) | DBIT(4, 1)); |
| 1201 | + out_be32(GPIO_DATA_RB333(reg), in_be32(GPIO_DATA_RB333(reg)) & ~SBIT(4)); |
| 1202 | + break; |
| 1203 | + case 6: |
| 1204 | + reg = ioremap(get_immrbase(), 0x1000); |
| 1205 | + local_irq_disable(); |
| 1206 | + out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000); |
| 1207 | + out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2)); |
| 1208 | + out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2)); |
| 1209 | + break; |
| 1210 | + default: |
| 1211 | + mpc83xx_restart(cmd); |
| 1212 | + break; |
| 1213 | + } |
| 1214 | + } |
| 1215 | + else mpc83xx_restart(cmd); |
| 1216 | + |
| 1217 | + for (;;) ; |
| 1218 | +} |
| 1219 | + |
| 1220 | +static void rbppc_halt(void) |
| 1221 | +{ |
| 1222 | + while (1); |
| 1223 | +} |
| 1224 | + |
| 1225 | +static struct of_device_id rbppc_ids[] = { |
| 1226 | + { .type = "soc", }, |
| 1227 | + { .compatible = "soc", }, |
| 1228 | + { .compatible = "simple-bus", }, |
| 1229 | + { .type = "qe", }, |
| 1230 | + { .compatible = "fsl,qe", }, |
| 1231 | + { .compatible = "gianfar", }, |
| 1232 | + { }, |
| 1233 | +}; |
| 1234 | + |
| 1235 | +static int __init rbppc_declare_of_platform_devices(void) |
| 1236 | +{ |
| 1237 | + struct device_node *np; |
| 1238 | + unsigned idx; |
| 1239 | + |
| 1240 | + of_platform_bus_probe(NULL, rbppc_ids, NULL); |
| 1241 | + |
| 1242 | + np = of_find_node_by_type(NULL, "mdio"); |
| 1243 | + if (np) { |
| 1244 | + unsigned len; |
| 1245 | + unsigned *res; |
| 1246 | + const unsigned *eres; |
| 1247 | + struct device_node *ep; |
| 1248 | + |
| 1249 | + ep = of_find_compatible_node(NULL, "network", "ucc_geth"); |
| 1250 | + if (ep) { |
| 1251 | + eres = of_get_property(ep, "reg", &len); |
| 1252 | + res = (unsigned *) of_get_property(np, "reg", &len); |
| 1253 | + if (res && eres) { |
| 1254 | + res[0] = eres[0] + 0x120; |
| 1255 | + } |
| 1256 | + } |
| 1257 | + } |
| 1258 | + |
| 1259 | + np = of_find_node_by_name(NULL, "nand"); |
| 1260 | + if (np) { |
| 1261 | + of_platform_device_create(np, "nand", NULL); |
| 1262 | + } |
| 1263 | + |
| 1264 | + idx = 0; |
| 1265 | + for_each_node_by_type(np, "rb,cf") { |
| 1266 | + char dev_name[12]; |
| 1267 | + snprintf(dev_name, sizeof(dev_name), "cf.%u", idx); |
| 1268 | + of_platform_device_create(np, dev_name, NULL); |
| 1269 | + ++idx; |
| 1270 | + } |
| 1271 | + |
| 1272 | + np = of_find_node_by_name(NULL, "beeper"); |
| 1273 | + if (np) { |
| 1274 | + rbppc_beeper_init(np); |
| 1275 | + } |
| 1276 | + |
| 1277 | + return 0; |
| 1278 | +} |
| 1279 | +machine_device_initcall(rb600, rbppc_declare_of_platform_devices); |
| 1280 | + |
| 1281 | +define_machine(rb600) { |
| 1282 | + .name = "MikroTik RouterBOARD 333/600 series", |
| 1283 | + .probe = rbppc_probe, |
| 1284 | + .setup_arch = rbppc_setup_arch, |
| 1285 | + .init_IRQ = rbppc_init_IRQ, |
| 1286 | + .get_irq = ipic_get_irq, |
| 1287 | + .restart = rbppc_restart, |
| 1288 | + .halt = rbppc_halt, |
| 1289 | + .time_init = mpc83xx_time_init, |
| 1290 | + .calibrate_decr = generic_calibrate_decr, |
| 1291 | +}; |
| 1292 | + |
| 1293 | +static void fixup_pcibridge(struct pci_dev *dev) |
| 1294 | +{ |
| 1295 | + if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { |
| 1296 | + /* let the kernel itself set right memory windows */ |
| 1297 | + pci_write_config_word(dev, PCI_MEMORY_BASE, 0); |
| 1298 | + pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0); |
| 1299 | + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0); |
| 1300 | + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0); |
| 1301 | + pci_write_config_byte(dev, PCI_IO_BASE, 0); |
| 1302 | + pci_write_config_byte(dev, PCI_IO_LIMIT, 4 << 4); |
| 1303 | + |
| 1304 | + pci_write_config_byte( |
| 1305 | + dev, PCI_COMMAND, |
| 1306 | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 1307 | + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); |
| 1308 | + } |
| 1309 | +} |
| 1310 | + |
| 1311 | + |
| 1312 | +static void fixup_rb604(struct pci_dev *dev) |
| 1313 | +{ |
| 1314 | + pci_write_config_byte(dev, 0xC0, 0x01); |
| 1315 | +} |
| 1316 | + |
| 1317 | +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_pcibridge) |
| 1318 | +DECLARE_PCI_FIXUP_HEADER(0x3388, 0x0021, fixup_rb604) |
| 1319 | |
