| 1 | /* |
| 2 | * Ralink RT288x SoC specific definitions |
| 3 | * |
| 4 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> |
| 5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
| 6 | * |
| 7 | * Parts of this file are based on Ralink's 2.6.21 BSP |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License version 2 as published |
| 11 | * by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #ifndef _RT288X_H_ |
| 15 | #define _RT288X_H_ |
| 16 | |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/io.h> |
| 19 | |
| 20 | #define RT288X_MEM_SIZE_MIN (2 * 1024 * 1024) |
| 21 | #define RT288X_MEM_SIZE_MAX (128 * 1024 * 1024) |
| 22 | |
| 23 | #define RT288X_CPU_IRQ_BASE 0 |
| 24 | #define RT288X_INTC_IRQ_BASE 8 |
| 25 | #define RT288X_INTC_IRQ_COUNT 32 |
| 26 | #define RT288X_GPIO_IRQ_BASE 40 |
| 27 | |
| 28 | #define RT288X_CPU_IRQ_INTC (RT288X_CPU_IRQ_BASE + 2) |
| 29 | #define RT288X_CPU_IRQ_PCI (RT288X_CPU_IRQ_BASE + 4) |
| 30 | #define RT288X_CPU_IRQ_FE (RT288X_CPU_IRQ_BASE + 5) |
| 31 | #define RT288X_CPU_IRQ_WNIC (RT288X_CPU_IRQ_BASE + 6) |
| 32 | #define RT288X_CPU_IRQ_COUNTER (RT288X_CPU_IRQ_BASE + 7) |
| 33 | |
| 34 | #define RT2880_INTC_IRQ_TIMER0 (RT288X_INTC_IRQ_BASE + 0) |
| 35 | #define RT2880_INTC_IRQ_TIMER1 (RT288X_INTC_IRQ_BASE + 1) |
| 36 | #define RT2880_INTC_IRQ_UART0 (RT288X_INTC_IRQ_BASE + 2) |
| 37 | #define RT2880_INTC_IRQ_PIO (RT288X_INTC_IRQ_BASE + 3) |
| 38 | #define RT2880_INTC_IRQ_PCM (RT288X_INTC_IRQ_BASE + 4) |
| 39 | #define RT2880_INTC_IRQ_UART1 (RT288X_INTC_IRQ_BASE + 8) |
| 40 | #define RT2880_INTC_IRQ_IA (RT288X_INTC_IRQ_BASE + 23) |
| 41 | |
| 42 | #define RT288X_GPIO_IRQ(x) (RT288X_GPIO_IRQ_BASE + (x)) |
| 43 | #define RT288X_GPIO_COUNT 32 |
| 44 | |
| 45 | extern void __iomem *rt288x_sysc_base; |
| 46 | extern void __iomem *rt288x_memc_base; |
| 47 | |
| 48 | static inline void rt288x_sysc_wr(u32 val, unsigned reg) |
| 49 | { |
| 50 | __raw_writel(val, rt288x_sysc_base + reg); |
| 51 | } |
| 52 | |
| 53 | static inline u32 rt288x_sysc_rr(unsigned reg) |
| 54 | { |
| 55 | return __raw_readl(rt288x_sysc_base + reg); |
| 56 | } |
| 57 | |
| 58 | static inline void rt288x_memc_wr(u32 val, unsigned reg) |
| 59 | { |
| 60 | __raw_writel(val, rt288x_memc_base + reg); |
| 61 | } |
| 62 | |
| 63 | static inline u32 rt288x_memc_rr(unsigned reg) |
| 64 | { |
| 65 | return __raw_readl(rt288x_memc_base + reg); |
| 66 | } |
| 67 | |
| 68 | void rt288x_gpio_init(u32 mode); |
| 69 | |
| 70 | #ifdef CONFIG_PCI |
| 71 | int rt288x_register_pci(void); |
| 72 | #else |
| 73 | static inline int rt288x_register_pci(void) { return 0; } |
| 74 | #endif /* CONFIG_PCI */ |
| 75 | |
| 76 | #endif /* _RT228X_H_ */ |
| 77 | |
