| 1 | /* |
| 2 | * Ralink RT305 SoC register definitions |
| 3 | * |
| 4 | * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #ifndef _RT305X_REGS_H_ |
| 12 | #define _RT305X_REGS_H_ |
| 13 | |
| 14 | #include <linux/bitops.h> |
| 15 | |
| 16 | #define RT305X_SDRAM_BASE 0x00000000 |
| 17 | #define RT305X_SYSC_BASE 0x10000000 |
| 18 | #define RT305X_TIMER_BASE 0x10000100 |
| 19 | #define RT305X_INTC_BASE 0x10000200 |
| 20 | #define RT305X_MEMC_BASE 0x10000300 |
| 21 | #define RT305X_PCM_BASE 0x10000400 |
| 22 | #define RT305X_UART0_BASE 0x10000500 |
| 23 | #define RT305X_PIO_BASE 0x10000600 |
| 24 | #define RT305X_GDMA_BASE 0x10000700 |
| 25 | #define RT305X_NANDC_BASE 0x10000800 |
| 26 | #define RT305X_I2C_BASE 0x10000900 |
| 27 | #define RT305X_I2S_BASE 0x10000a00 |
| 28 | #define RT305X_SPI_BASE 0x10000b00 |
| 29 | #define RT305X_UART1_BASE 0x10000c00 |
| 30 | #define RT305X_FE_BASE 0x10100000 |
| 31 | #define RT305X_SWITCH_BASE 0x10110000 |
| 32 | #define RT305X_WMAC_BASE 0x10180000 |
| 33 | #define RT305X_OTG_BASE 0x101c0000 |
| 34 | #define RT305X_ROM_BASE 0x00400000 |
| 35 | #define RT305X_FLASH1_BASE 0x1b000000 |
| 36 | #define RT305X_FLASH0_BASE 0x1f000000 |
| 37 | |
| 38 | #define RT305X_SYSC_SIZE 0x100 |
| 39 | #define RT305X_TIMER_SIZE 0x100 |
| 40 | #define RT305X_INTC_SIZE 0x100 |
| 41 | #define RT305X_MEMC_SIZE 0x100 |
| 42 | #define RT305X_UART0_SIZE 0x100 |
| 43 | #define RT305X_PIO_SIZE 0x100 |
| 44 | #define RT305X_UART1_SIZE 0x100 |
| 45 | #define RT305X_SPI_SIZE 0x100 |
| 46 | #define RT305X_FLASH1_SIZE (16 * 1024 * 1024) |
| 47 | #define RT305X_FLASH0_SIZE (8 * 1024 * 1024) |
| 48 | |
| 49 | #define RT3352_EHCI_BASE 0x101c0000 |
| 50 | #define RT3352_EHCI_SIZE 0x1000 |
| 51 | #define RT3352_OHCI_BASE 0x101c1000 |
| 52 | #define RT3352_OHCI_SIZE 0x1000 |
| 53 | |
| 54 | /* SYSC registers */ |
| 55 | #define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */ |
| 56 | #define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */ |
| 57 | #define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */ |
| 58 | #define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */ |
| 59 | #define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/ |
| 60 | #define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/ |
| 61 | #define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */ |
| 62 | #define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */ |
| 63 | #define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */ |
| 64 | |
| 65 | #define RT3352_SYSC_REG_SYSCFG1 0x014 |
| 66 | #define RT3352_SYSC_REG_CLKCFG1 0x030 |
| 67 | #define RT3352_SYSC_REG_RSTCTRL 0x034 |
| 68 | #define RT3352_SYSC_REG_USB_PS 0x05c |
| 69 | |
| 70 | #define RT3052_CHIP_NAME0 0x30335452 |
| 71 | #define RT3052_CHIP_NAME1 0x20203235 |
| 72 | |
| 73 | #define RT3350_CHIP_NAME0 0x33335452 |
| 74 | #define RT3350_CHIP_NAME1 0x20203035 |
| 75 | |
| 76 | #define RT3352_CHIP_NAME0 0x33335452 |
| 77 | #define RT3352_CHIP_NAME1 0x20203235 |
| 78 | |
| 79 | #define RT5350_CHIP_NAME0 0x33355452 |
| 80 | #define RT5350_CHIP_NAME1 0x20203035 |
| 81 | |
| 82 | #define CHIP_ID_ID_MASK 0xff |
| 83 | #define CHIP_ID_ID_SHIFT 8 |
| 84 | #define CHIP_ID_REV_MASK 0xff |
| 85 | |
| 86 | #define RT305X_SYSCFG_CPUCLK_SHIFT 18 |
| 87 | #define RT305X_SYSCFG_CPUCLK_MASK 0x1 |
| 88 | #define RT305X_SYSCFG_CPUCLK_LOW 0x0 |
| 89 | #define RT305X_SYSCFG_CPUCLK_HIGH 0x1 |
| 90 | #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 |
| 91 | #define RT305X_SYSCFG_SRAM_CS0_MODE_MASK 0x3 |
| 92 | #define RT305X_SYSCFG_SRAM_CS0_MODE_NORMAL 0 |
| 93 | #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 1 |
| 94 | #define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX 2 |
| 95 | |
| 96 | #define RT3352_SYSCFG0_CPUCLK_SHIFT 8 |
| 97 | #define RT3352_SYSCFG0_CPUCLK_MASK 0x1 |
| 98 | #define RT3352_SYSCFG0_CPUCLK_LOW 0x0 |
| 99 | #define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 |
| 100 | |
| 101 | #define RT5350_SYSCFG0_CPUCLK_SHIFT 8 |
| 102 | #define RT5350_SYSCFG0_CPUCLK_MASK 0x3 |
| 103 | #define RT5350_SYSCFG0_CPUCLK_360 0x0 |
| 104 | #define RT5350_SYSCFG0_CPUCLK_320 0x2 |
| 105 | #define RT5350_SYSCFG0_CPUCLK_300 0x3 |
| 106 | #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12 |
| 107 | #define RT5350_SYSCFG0_DRAM_SIZE_MASK 7 |
| 108 | #define RT5350_SYSCFG0_DRAM_SIZE_2M 0 |
| 109 | #define RT5350_SYSCFG0_DRAM_SIZE_8M 1 |
| 110 | #define RT5350_SYSCFG0_DRAM_SIZE_16M 2 |
| 111 | #define RT5350_SYSCFG0_DRAM_SIZE_32M 3 |
| 112 | #define RT5350_SYSCFG0_DRAM_SIZE_64M 4 |
| 113 | |
| 114 | #define RT3352_SYSCFG0_XTAL_SEL BIT(20) |
| 115 | |
| 116 | #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) |
| 117 | |
| 118 | #define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) |
| 119 | #define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) |
| 120 | |
| 121 | #define RT305X_GPIO_MODE_I2C BIT(0) |
| 122 | #define RT305X_GPIO_MODE_SPI BIT(1) |
| 123 | #define RT305X_GPIO_MODE_UART0_SHIFT 2 |
| 124 | #define RT305X_GPIO_MODE_UART0_MASK 0x7 |
| 125 | #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) |
| 126 | #define RT305X_GPIO_MODE_UARTF 0x0 |
| 127 | #define RT305X_GPIO_MODE_PCM_UARTF 0x1 |
| 128 | #define RT305X_GPIO_MODE_PCM_I2S 0x2 |
| 129 | #define RT305X_GPIO_MODE_I2S_UARTF 0x3 |
| 130 | #define RT305X_GPIO_MODE_PCM_GPIO 0x4 |
| 131 | #define RT305X_GPIO_MODE_GPIO_UARTF 0x5 |
| 132 | #define RT305X_GPIO_MODE_GPIO_I2S 0x6 |
| 133 | #define RT305X_GPIO_MODE_GPIO 0x7 |
| 134 | #define RT305X_GPIO_MODE_UART1 BIT(5) |
| 135 | #define RT305X_GPIO_MODE_JTAG BIT(6) |
| 136 | #define RT305X_GPIO_MODE_MDIO BIT(7) |
| 137 | #define RT305X_GPIO_MODE_SDRAM BIT(8) |
| 138 | #define RT305X_GPIO_MODE_RGMII BIT(9) |
| 139 | |
| 140 | #define RT305X_RESET_SYSTEM BIT(0) |
| 141 | #define RT305X_RESET_TIMER BIT(8) |
| 142 | #define RT305X_RESET_INTC BIT(9) |
| 143 | #define RT305X_RESET_MEMC BIT(10) |
| 144 | #define RT305X_RESET_PCM BIT(11) |
| 145 | #define RT305X_RESET_UART0 BIT(12) |
| 146 | #define RT305X_RESET_PIO BIT(13) |
| 147 | #define RT305X_RESET_DMA BIT(14) |
| 148 | #define RT305X_RESET_I2C BIT(16) |
| 149 | #define RT305X_RESET_I2S BIT(17) |
| 150 | #define RT305X_RESET_SPI BIT(18) |
| 151 | #define RT305X_RESET_UART1 BIT(19) |
| 152 | #define RT305X_RESET_WNIC BIT(20) |
| 153 | #define RT305X_RESET_FE BIT(21) |
| 154 | #define RT305X_RESET_OTG BIT(22) |
| 155 | #define RT305X_RESET_ESW BIT(23) |
| 156 | |
| 157 | #define RT3352_RSTCTRL_SYS BIT(0) |
| 158 | #define RT3352_RSTCTRL_TIMER BIT(8) |
| 159 | #define RT3352_RSTCTRL_INTC BIT(9) |
| 160 | #define RT3352_RSTCTRL_MEMC BIT(10) |
| 161 | #define RT3352_RSTCTRL_PCM BIT(11) |
| 162 | #define RT3352_RSTCTRL_UART0 BIT(12) |
| 163 | #define RT3352_RSTCTRL_PIO BIT(13) |
| 164 | #define RT3352_RSTCTRL_DMA BIT(14) |
| 165 | #define RT3352_RSTCTRL_I2C BIT(16) |
| 166 | #define RT3352_RSTCTRL_I2S BIT(17) |
| 167 | #define RT3352_RSTCTRL_SPI BIT(18) |
| 168 | #define RT3352_RSTCTRL_UART1 BIT(19) |
| 169 | #define RT3352_RSTCTRL_WNIC BIT(20) |
| 170 | #define RT3352_RSTCTRL_FE BIT(21) |
| 171 | #define RT3352_RSTCTRL_UHST BIT(22) |
| 172 | #define RT3352_RSTCTRL_ESW BIT(23) |
| 173 | #define RT3352_RSTCTRL_EPHY BIT(24) |
| 174 | #define RT3352_RSTCTRL_UDEV BIT(25) |
| 175 | |
| 176 | #define RT305X_INTC_INT_SYSCTL BIT(0) |
| 177 | #define RT305X_INTC_INT_TIMER0 BIT(1) |
| 178 | #define RT305X_INTC_INT_TIMER1 BIT(2) |
| 179 | #define RT305X_INTC_INT_IA BIT(3) |
| 180 | #define RT305X_INTC_INT_PCM BIT(4) |
| 181 | #define RT305X_INTC_INT_UART0 BIT(5) |
| 182 | #define RT305X_INTC_INT_PIO BIT(6) |
| 183 | #define RT305X_INTC_INT_DMA BIT(7) |
| 184 | #define RT305X_INTC_INT_NAND BIT(8) |
| 185 | #define RT305X_INTC_INT_PERFC BIT(9) |
| 186 | #define RT305X_INTC_INT_I2S BIT(10) |
| 187 | #define RT305X_INTC_INT_UART1 BIT(12) |
| 188 | #define RT305X_INTC_INT_ESW BIT(17) |
| 189 | #define RT305X_INTC_INT_OTG BIT(18) |
| 190 | #define RT305X_INTC_INT_GLOBAL BIT(31) |
| 191 | |
| 192 | /* MEMC registers */ |
| 193 | #define MEMC_REG_SDRAM_CFG0 0x00 |
| 194 | #define MEMC_REG_SDRAM_CFG1 0x04 |
| 195 | #define MEMC_REG_FLASH_CFG0 0x08 |
| 196 | #define MEMC_REG_FLASH_CFG1 0x0c |
| 197 | #define MEMC_REG_IA_ADDR 0x10 |
| 198 | #define MEMC_REG_IA_TYPE 0x14 |
| 199 | |
| 200 | #define FLASH_CFG_WIDTH_SHIFT 26 |
| 201 | #define FLASH_CFG_WIDTH_MASK 0x3 |
| 202 | #define FLASH_CFG_WIDTH_8BIT 0x0 |
| 203 | #define FLASH_CFG_WIDTH_16BIT 0x1 |
| 204 | #define FLASH_CFG_WIDTH_32BIT 0x2 |
| 205 | |
| 206 | /* UART registers */ |
| 207 | #define UART_REG_RX 0 |
| 208 | #define UART_REG_TX 1 |
| 209 | #define UART_REG_IER 2 |
| 210 | #define UART_REG_IIR 3 |
| 211 | #define UART_REG_FCR 4 |
| 212 | #define UART_REG_LCR 5 |
| 213 | #define UART_REG_MCR 6 |
| 214 | #define UART_REG_LSR 7 |
| 215 | |
| 216 | #endif /* _RT305X_REGS_H_ */ |
| 217 | |
