Root/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883.h

1/*
2 * Ralink RT3662/RT3883 SoC specific definitions
3 *
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#ifndef _RT3883_H_
14#define _RT3883_H_
15
16#include <linux/init.h>
17#include <linux/io.h>
18
19#define RT3883_MEM_SIZE_MIN (2 * 1024 * 1024)
20#define RT3883_MEM_SIZE_MAX (256 * 1024 * 1024)
21
22#define RT3883_CPU_IRQ_BASE 0
23#define RT3883_CPU_IRQ_COUNT 8
24#define RT3883_INTC_IRQ_BASE (RT3883_CPU_IRQ_BASE + RT3883_CPU_IRQ_COUNT)
25#define RT3883_INTC_IRQ_COUNT 32
26#define RT3883_GPIO_IRQ_BASE (RT3883_INTC_IRQ_BASE + RT3883_INTC_IRQ_COUNT)
27#define RT3883_GPIO_IRQ_COUNT 96
28#define RT3883_PCI_IRQ_BASE (RT3883_GPIO_IRQ_BASE + RT3883_GPIO_IRQ_COUNT)
29#define RT3883_PCI_IRQ_COUNT 3
30
31#define RT3883_CPU_IRQ_INTC (RT3883_CPU_IRQ_BASE + 2)
32#define RT3883_CPU_IRQ_PCI (RT3883_CPU_IRQ_BASE + 4)
33#define RT3883_CPU_IRQ_FE (RT3883_CPU_IRQ_BASE + 5)
34#define RT3883_CPU_IRQ_WLAN (RT3883_CPU_IRQ_BASE + 6)
35#define RT3883_CPU_IRQ_COUNTER (RT3883_CPU_IRQ_BASE + 7)
36
37#define RT3883_INTC_IRQ_SYSCTL (RT3883_INTC_IRQ_BASE + 0)
38#define RT3883_INTC_IRQ_TIMER0 (RT3883_INTC_IRQ_BASE + 1)
39#define RT3883_INTC_IRQ_TIMER1 (RT3883_INTC_IRQ_BASE + 2)
40#define RT3883_INTC_IRQ_IA (RT3883_INTC_IRQ_BASE + 3)
41#define RT3883_INTC_IRQ_PCM (RT3883_INTC_IRQ_BASE + 4)
42#define RT3883_INTC_IRQ_UART0 (RT3883_INTC_IRQ_BASE + 5)
43#define RT3883_INTC_IRQ_PIO (RT3883_INTC_IRQ_BASE + 6)
44#define RT3883_INTC_IRQ_DMA (RT3883_INTC_IRQ_BASE + 7)
45#define RT3883_INTC_IRQ_NAND (RT3883_INTC_IRQ_BASE + 8)
46#define RT3883_INTC_IRQ_PERFC (RT3883_INTC_IRQ_BASE + 9)
47#define RT3883_INTC_IRQ_I2S (RT3883_INTC_IRQ_BASE + 10)
48#define RT3883_INTC_IRQ_UART1 (RT3883_INTC_IRQ_BASE + 12)
49#define RT3883_INTC_IRQ_UHST (RT3883_INTC_IRQ_BASE + 18)
50#define RT3883_INTC_IRQ_UDEV (RT3883_INTC_IRQ_BASE + 19)
51
52#define RT3883_PCI_IRQ_PCI0 (RT3883_PCI_IRQ_BASE + 0)
53#define RT3883_PCI_IRQ_PCI1 (RT3883_PCI_IRQ_BASE + 1)
54#define RT3883_PCI_IRQ_PCIE (RT3883_PCI_IRQ_BASE + 2)
55
56extern void __iomem *rt3883_sysc_base;
57extern void __iomem *rt3883_memc_base;
58
59static inline void rt3883_sysc_wr(u32 val, unsigned reg)
60{
61    __raw_writel(val, rt3883_sysc_base + reg);
62}
63
64static inline u32 rt3883_sysc_rr(unsigned reg)
65{
66    return __raw_readl(rt3883_sysc_base + reg);
67}
68
69static inline void rt3883_memc_wr(u32 val, unsigned reg)
70{
71    __raw_writel(val, rt3883_memc_base + reg);
72}
73
74static inline u32 rt3883_memc_rr(unsigned reg)
75{
76    return __raw_readl(rt3883_memc_base + reg);
77}
78
79#define RT3883_GPIO_I2C_SD 1
80#define RT3883_GPIO_I2C_SCLK 2
81#define RT3883_GPIO_SPI_CS0 3
82#define RT3883_GPIO_SPI_CLK 4
83#define RT3883_GPIO_SPI_MOSI 5
84#define RT3883_GPIO_SPI_MISO 6
85/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
86#define RT3883_GPIO_7 7
87#define RT3883_GPIO_8 8
88#define RT3883_GPIO_9 9
89#define RT3883_GPIO_10 10
90#define RT3883_GPIO_11 11
91#define RT3883_GPIO_12 12
92#define RT3883_GPIO_13 13
93#define RT3883_GPIO_14 14
94#define RT3883_GPIO_UART1_TXD 15
95#define RT3883_GPIO_UART1_RXD 16
96#define RT3883_GPIO_JTAG_TDO 17
97#define RT3883_GPIO_JTAG_TDI 18
98#define RT3883_GPIO_JTAG_TMS 19
99#define RT3883_GPIO_JTAG_TCLK 20
100#define RT3883_GPIO_JTAG_TRST_N 21
101#define RT3883_GPIO_MDIO_MDC 22
102#define RT3883_GPIO_MDIO_MDIO 23
103#define RT3883_GPIO_LNA_PE_A0 32
104#define RT3883_GPIO_LNA_PE_A1 33
105#define RT3883_GPIO_LNA_PE_A2 34
106#define RT3883_GPIO_LNA_PE_G0 35
107#define RT3883_GPIO_LNA_PE_G1 36
108#define RT3883_GPIO_LNA_PE_G2 37
109#define RT3883_GPIO_PCI_AD0 40
110#define RT3883_GPIO_PCI_AD31 71
111#define RT3883_GPIO_GE2_TXD0 72
112#define RT3883_GPIO_GE2_TXD1 73
113#define RT3883_GPIO_GE2_TXD2 74
114#define RT3883_GPIO_GE2_TXD3 75
115#define RT3883_GPIO_GE2_TXEN 76
116#define RT3883_GPIO_GE2_TXCLK 77
117#define RT3883_GPIO_GE2_RXD0 78
118#define RT3883_GPIO_GE2_RXD1 79
119#define RT3883_GPIO_GE2_RXD2 80
120#define RT3883_GPIO_GE2_RXD3 81
121#define RT3883_GPIO_GE2_RXDV 82
122#define RT3883_GPIO_GE2_RXCLK 83
123#define RT3883_GPIO_GE1_TXD0 84
124#define RT3883_GPIO_GE1_TXD1 85
125#define RT3883_GPIO_GE1_TXD2 86
126#define RT3883_GPIO_GE1_TXD3 87
127#define RT3883_GPIO_GE1_TXEN 88
128#define RT3883_GPIO_GE1_TXCLK 89
129#define RT3883_GPIO_GE1_RXD0 90
130#define RT3883_GPIO_GE1_RXD1 91
131#define RT3883_GPIO_GE1_RXD2 92
132#define RT3883_GPIO_GE1_RXD3 93
133#define RT3883_GPIO_GE1_RXDV 94
134#define RT3883_GPIO_GE1_RXCLK 95
135
136void rt3883_gpio_init(u32 mode);
137
138#define RT3883_PCI_MODE_PCI 0x01
139#define RT3883_PCI_MODE_PCIE 0x02
140#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
141
142struct pci_dev;
143
144#ifdef CONFIG_PCI
145void rt3883_pci_init(unsigned mode);
146void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *));
147#else
148static inline void rt3883_pci_init(unsigned mode) {}
149static inline void rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *)) {}
150#endif /* CONFIG_PCI */
151
152#endif /* _RT3883_H_ */
153

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