| 1 | /* |
| 2 | * Ralink RT305X clock API |
| 3 | * |
| 4 | * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/clk.h> |
| 16 | |
| 17 | #include <asm/mach-ralink/common.h> |
| 18 | #include <asm/mach-ralink/rt305x.h> |
| 19 | #include <asm/mach-ralink/rt305x_regs.h> |
| 20 | #include "common.h" |
| 21 | |
| 22 | struct clk { |
| 23 | unsigned long rate; |
| 24 | }; |
| 25 | |
| 26 | static struct clk rt305x_cpu_clk; |
| 27 | static struct clk rt305x_sys_clk; |
| 28 | static struct clk rt305x_wdt_clk; |
| 29 | static struct clk rt305x_uart_clk; |
| 30 | |
| 31 | void __init rt305x_clocks_init(void) |
| 32 | { |
| 33 | u32 t; |
| 34 | |
| 35 | t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); |
| 36 | |
| 37 | if (soc_is_rt305x() || soc_is_rt3350()) { |
| 38 | t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & |
| 39 | RT305X_SYSCFG_CPUCLK_MASK; |
| 40 | switch (t) { |
| 41 | case RT305X_SYSCFG_CPUCLK_LOW: |
| 42 | rt305x_cpu_clk.rate = 320000000; |
| 43 | break; |
| 44 | case RT305X_SYSCFG_CPUCLK_HIGH: |
| 45 | rt305x_cpu_clk.rate = 384000000; |
| 46 | break; |
| 47 | } |
| 48 | rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; |
| 49 | rt305x_uart_clk.rate = rt305x_sys_clk.rate; |
| 50 | rt305x_wdt_clk.rate = rt305x_sys_clk.rate; |
| 51 | } else if (soc_is_rt3352()) { |
| 52 | t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & |
| 53 | RT3352_SYSCFG0_CPUCLK_MASK; |
| 54 | switch (t) { |
| 55 | case RT3352_SYSCFG0_CPUCLK_LOW: |
| 56 | rt305x_cpu_clk.rate = 384000000; |
| 57 | break; |
| 58 | case RT3352_SYSCFG0_CPUCLK_HIGH: |
| 59 | rt305x_cpu_clk.rate = 400000000; |
| 60 | break; |
| 61 | } |
| 62 | rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; |
| 63 | rt305x_uart_clk.rate = 40000000; |
| 64 | rt305x_wdt_clk.rate = rt305x_sys_clk.rate; |
| 65 | } else if (soc_is_rt5350()) { |
| 66 | t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & |
| 67 | RT5350_SYSCFG0_CPUCLK_MASK; |
| 68 | switch (t) { |
| 69 | case RT5350_SYSCFG0_CPUCLK_360: |
| 70 | rt305x_cpu_clk.rate = 360000000; |
| 71 | rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; |
| 72 | break; |
| 73 | case RT5350_SYSCFG0_CPUCLK_320: |
| 74 | rt305x_cpu_clk.rate = 320000000; |
| 75 | rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 4; |
| 76 | break; |
| 77 | case RT5350_SYSCFG0_CPUCLK_300: |
| 78 | rt305x_cpu_clk.rate = 300000000; |
| 79 | rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; |
| 80 | break; |
| 81 | default: |
| 82 | BUG(); |
| 83 | } |
| 84 | rt305x_uart_clk.rate = 40000000; |
| 85 | rt305x_wdt_clk.rate = rt305x_sys_clk.rate; |
| 86 | } else { |
| 87 | BUG(); |
| 88 | } |
| 89 | |
| 90 | } |
| 91 | |
| 92 | /* |
| 93 | * Linux clock API |
| 94 | */ |
| 95 | struct clk *clk_get(struct device *dev, const char *id) |
| 96 | { |
| 97 | if (!strcmp(id, "sys")) |
| 98 | return &rt305x_sys_clk; |
| 99 | |
| 100 | if (!strcmp(id, "cpu")) |
| 101 | return &rt305x_cpu_clk; |
| 102 | |
| 103 | if (!strcmp(id, "wdt")) |
| 104 | return &rt305x_wdt_clk; |
| 105 | |
| 106 | if (!strcmp(id, "uart")) |
| 107 | return &rt305x_uart_clk; |
| 108 | |
| 109 | return ERR_PTR(-ENOENT); |
| 110 | } |
| 111 | EXPORT_SYMBOL(clk_get); |
| 112 | |
| 113 | int clk_enable(struct clk *clk) |
| 114 | { |
| 115 | return 0; |
| 116 | } |
| 117 | EXPORT_SYMBOL(clk_enable); |
| 118 | |
| 119 | void clk_disable(struct clk *clk) |
| 120 | { |
| 121 | } |
| 122 | EXPORT_SYMBOL(clk_disable); |
| 123 | |
| 124 | unsigned long clk_get_rate(struct clk *clk) |
| 125 | { |
| 126 | return clk->rate; |
| 127 | } |
| 128 | EXPORT_SYMBOL(clk_get_rate); |
| 129 | |
| 130 | void clk_put(struct clk *clk) |
| 131 | { |
| 132 | } |
| 133 | EXPORT_SYMBOL(clk_put); |
| 134 | |
