| 1 | /* |
| 2 | * Ralink RT305x SoC specific setup |
| 3 | * |
| 4 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> |
| 5 | * |
| 6 | * Parts of this file are based on Ralink's 2.6.21 BSP |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License version 2 as published |
| 10 | * by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/clk.h> |
| 18 | |
| 19 | #include <asm/mips_machine.h> |
| 20 | #include <asm/reboot.h> |
| 21 | #include <asm/time.h> |
| 22 | |
| 23 | #include <asm/mach-ralink/common.h> |
| 24 | #include <asm/mach-ralink/rt305x.h> |
| 25 | #include <asm/mach-ralink/rt305x_regs.h> |
| 26 | #include "common.h" |
| 27 | |
| 28 | static void rt305x_restart(char *command) |
| 29 | { |
| 30 | rt305x_sysc_wr(RT305X_RESET_SYSTEM, SYSC_REG_RESET_CTRL); |
| 31 | while (1) |
| 32 | if (cpu_wait) |
| 33 | cpu_wait(); |
| 34 | } |
| 35 | |
| 36 | static void rt305x_halt(void) |
| 37 | { |
| 38 | while (1) |
| 39 | if (cpu_wait) |
| 40 | cpu_wait(); |
| 41 | } |
| 42 | |
| 43 | unsigned int __cpuinit get_c0_compare_irq(void) |
| 44 | { |
| 45 | return CP0_LEGACY_COMPARE_IRQ; |
| 46 | } |
| 47 | |
| 48 | void __init ramips_soc_setup(void) |
| 49 | { |
| 50 | struct clk *clk; |
| 51 | |
| 52 | rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE); |
| 53 | rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE); |
| 54 | |
| 55 | rt305x_clocks_init(); |
| 56 | |
| 57 | clk = clk_get(NULL, "cpu"); |
| 58 | if (IS_ERR(clk)) |
| 59 | panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); |
| 60 | |
| 61 | printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type, |
| 62 | clk_get_rate(clk) / 1000000, |
| 63 | (clk_get_rate(clk) % 1000000) * 100 / 1000000); |
| 64 | |
| 65 | _machine_restart = rt305x_restart; |
| 66 | _machine_halt = rt305x_halt; |
| 67 | pm_power_off = rt305x_halt; |
| 68 | |
| 69 | clk = clk_get(NULL, "uart"); |
| 70 | if (IS_ERR(clk)) |
| 71 | panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); |
| 72 | |
| 73 | ramips_early_serial_setup(0, RT305X_UART0_BASE, clk_get_rate(clk), |
| 74 | RT305X_INTC_IRQ_UART0); |
| 75 | ramips_early_serial_setup(1, RT305X_UART1_BASE, clk_get_rate(clk), |
| 76 | RT305X_INTC_IRQ_UART1); |
| 77 | } |
| 78 | |
| 79 | void __init plat_time_init(void) |
| 80 | { |
| 81 | struct clk *clk; |
| 82 | |
| 83 | clk = clk_get(NULL, "cpu"); |
| 84 | if (IS_ERR(clk)) |
| 85 | panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); |
| 86 | |
| 87 | mips_hpt_frequency = clk_get_rate(clk) / 2; |
| 88 | } |
| 89 | |
