| 1 | From 2dcb0ca66d0bffc23d5f001fad81fb1a7a2c371b Mon Sep 17 00:00:00 2001 |
| 2 | From: Maarten ter Huurne <maarten@treewalker.org> |
| 3 | Date: Tue, 28 Jun 2011 22:28:59 +0200 |
| 4 | Subject: [PATCH 14/21] MIPS: JZ4740: reset: Initialize hibernate wakeup |
| 5 | counters. |
| 6 | |
| 7 | In hibernation mode only the wakeup logic and the RTC are left running, |
| 8 | so this is what users perceive as power down. |
| 9 | |
| 10 | If the counters are not initialized, the corresponding pin (typically |
| 11 | connected to the power button) has to be asserted for two seconds |
| 12 | before the device wakes up. Most users expect a shorter wakeup time. |
| 13 | |
| 14 | I took the timing values of 100 ms and 60 ms from BouKiCHi's patch for |
| 15 | the Dingoo A320 kernel. |
| 16 | --- |
| 17 | arch/mips/jz4740/reset.c | 46 ++++++++++++++++++++++++++++++++++++++++------ |
| 18 | 1 files changed, 40 insertions(+), 6 deletions(-) |
| 19 | |
| 20 | --- a/arch/mips/jz4740/reset.c |
| 21 | +++ b/arch/mips/jz4740/reset.c |
| 22 | @@ -21,6 +21,9 @@ |
| 23 | #include <asm/mach-jz4740/base.h> |
| 24 | #include <asm/mach-jz4740/timer.h> |
| 25 | |
| 26 | +#include "reset.h" |
| 27 | +#include "clock.h" |
| 28 | + |
| 29 | static void jz4740_halt(void) |
| 30 | { |
| 31 | while (1) { |
| 32 | @@ -53,21 +56,52 @@ static void jz4740_restart(char *command |
| 33 | jz4740_halt(); |
| 34 | } |
| 35 | |
| 36 | -#define JZ_REG_RTC_CTRL 0x00 |
| 37 | -#define JZ_REG_RTC_HIBERNATE 0x20 |
| 38 | - |
| 39 | -#define JZ_RTC_CTRL_WRDY BIT(7) |
| 40 | +#define JZ_REG_RTC_CTRL 0x00 |
| 41 | +#define JZ_REG_RTC_HIBERNATE 0x20 |
| 42 | +#define JZ_REG_RTC_WAKEUP_FILTER 0x24 |
| 43 | +#define JZ_REG_RTC_RESET_COUNTER 0x28 |
| 44 | + |
| 45 | +#define JZ_RTC_CTRL_WRDY BIT(7) |
| 46 | +#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0 |
| 47 | +#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0 |
| 48 | |
| 49 | -static void jz4740_power_off(void) |
| 50 | +static inline void jz4740_rtc_wait_ready(void __iomem *rtc_base) |
| 51 | { |
| 52 | - void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24); |
| 53 | uint32_t ctrl; |
| 54 | - |
| 55 | do { |
| 56 | ctrl = readl(rtc_base + JZ_REG_RTC_CTRL); |
| 57 | } while (!(ctrl & JZ_RTC_CTRL_WRDY)); |
| 58 | +} |
| 59 | |
| 60 | +static void jz4740_power_off(void) |
| 61 | +{ |
| 62 | + void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38); |
| 63 | + unsigned long long wakeup_filter_ticks; |
| 64 | + unsigned long long reset_counter_ticks; |
| 65 | + |
| 66 | + /* Set minimum wakeup pin assertion time: 100 ms. |
| 67 | + Range is 0 to 2 sec if RTC is clocked at 32 kHz. */ |
| 68 | + wakeup_filter_ticks = (100 * jz4740_clock_bdata.rtc_rate) / 1000; |
| 69 | + if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK) |
| 70 | + wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK; |
| 71 | + else |
| 72 | + wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK; |
| 73 | + jz4740_rtc_wait_ready(rtc_base); |
| 74 | + writel(wakeup_filter_ticks, rtc_base + JZ_REG_RTC_WAKEUP_FILTER); |
| 75 | + |
| 76 | + /* Set reset pin low-level assertion time after wakeup: 60 ms. |
| 77 | + Range is 0 to 125 ms if RTC is clocked at 32 kHz. */ |
| 78 | + reset_counter_ticks = (60 * jz4740_clock_bdata.rtc_rate) / 1000; |
| 79 | + if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK) |
| 80 | + reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK; |
| 81 | + else |
| 82 | + reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK; |
| 83 | + jz4740_rtc_wait_ready(rtc_base); |
| 84 | + writel(reset_counter_ticks, rtc_base + JZ_REG_RTC_RESET_COUNTER); |
| 85 | + |
| 86 | + jz4740_rtc_wait_ready(rtc_base); |
| 87 | writel(1, rtc_base + JZ_REG_RTC_HIBERNATE); |
| 88 | + |
| 89 | jz4740_halt(); |
| 90 | } |
| 91 | |
| 92 | |
