Root/target/linux/generic-2.6/files/drivers/net/phy/rtl8366rb.c

1/*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/skbuff.h>
18#include <linux/rtl8366rb.h>
19
20#include "rtl8366_smi.h"
21
22#define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
23#define RTL8366RB_DRIVER_VER "0.2.2"
24
25#define RTL8366RB_PHY_NO_MAX 4
26#define RTL8366RB_PHY_PAGE_MAX 7
27#define RTL8366RB_PHY_ADDR_MAX 31
28
29/* Switch Global Configuration register */
30#define RTL8366RB_SGCR 0x0000
31#define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
32#define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
33#define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
34#define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
35#define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
36#define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
37#define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
38#define RTL8366RB_SGCR_EN_VLAN BIT(13)
39#define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
40
41/* Port Enable Control register */
42#define RTL8366RB_PECR 0x0001
43
44/* Switch Security Control registers */
45#define RTL8366RB_SSCR0 0x0002
46#define RTL8366RB_SSCR1 0x0003
47#define RTL8366RB_SSCR2 0x0004
48#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
49
50#define RTL8366RB_RESET_CTRL_REG 0x0100
51#define RTL8366RB_CHIP_CTRL_RESET_HW 1
52#define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
53
54#define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
55#define RTL8366RB_CHIP_VERSION_MASK 0xf
56#define RTL8366RB_CHIP_ID_REG 0x0509
57#define RTL8366RB_CHIP_ID_8366 0x5937
58
59/* PHY registers control */
60#define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
61#define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
62
63#define RTL8366RB_PHY_CTRL_READ 1
64#define RTL8366RB_PHY_CTRL_WRITE 0
65
66#define RTL8366RB_PHY_REG_MASK 0x1f
67#define RTL8366RB_PHY_PAGE_OFFSET 5
68#define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
69#define RTL8366RB_PHY_NO_OFFSET 9
70#define RTL8366RB_PHY_NO_MASK (0x1f << 9)
71
72#define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
73
74/* LED control registers */
75#define RTL8366RB_LED_BLINKRATE_REG 0x0430
76#define RTL8366RB_LED_BLINKRATE_BIT 0
77#define RTL8366RB_LED_BLINKRATE_MASK 0x0007
78
79#define RTL8366RB_LED_CTRL_REG 0x0431
80#define RTL8366RB_LED_0_1_CTRL_REG 0x0432
81#define RTL8366RB_LED_2_3_CTRL_REG 0x0433
82
83#define RTL8366RB_MIB_COUNT 33
84#define RTL8366RB_GLOBAL_MIB_COUNT 1
85#define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
86#define RTL8366RB_MIB_COUNTER_BASE 0x1000
87#define RTL8366RB_MIB_CTRL_REG 0x13F0
88#define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
89#define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
90#define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
91#define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
92#define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
93
94#define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
95#define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
96        (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
97#define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
98#define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
99
100
101#define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
102#define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
103
104
105#define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
106#define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
107#define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
108
109#define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
110
111
112#define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
113#define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
114#define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
115#define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
116#define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
117#define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
118#define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
119
120
121#define RTL8366RB_PORT_NUM_CPU 5
122#define RTL8366RB_NUM_PORTS 6
123#define RTL8366RB_NUM_VLANS 16
124#define RTL8366RB_NUM_LEDGROUPS 4
125#define RTL8366RB_NUM_VIDS 4096
126#define RTL8366RB_PRIORITYMAX 7
127#define RTL8366RB_FIDMAX 7
128
129
130#define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
131#define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
132#define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
133#define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
134#define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
135
136#define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
137
138#define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
139                     RTL8366RB_PORT_2 | \
140                     RTL8366RB_PORT_3 | \
141                     RTL8366RB_PORT_4 | \
142                     RTL8366RB_PORT_5 | \
143                     RTL8366RB_PORT_CPU)
144
145#define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
146                     RTL8366RB_PORT_2 | \
147                     RTL8366RB_PORT_3 | \
148                     RTL8366RB_PORT_4 | \
149                     RTL8366RB_PORT_5)
150
151#define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
152                     RTL8366RB_PORT_2 | \
153                     RTL8366RB_PORT_3 | \
154                     RTL8366RB_PORT_4)
155
156#define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
157
158#define RTL8366RB_VLAN_VID_MASK 0xfff
159#define RTL8366RB_VLAN_PRIORITY_SHIFT 12
160#define RTL8366RB_VLAN_PRIORITY_MASK 0x7
161#define RTL8366RB_VLAN_UNTAG_SHIFT 8
162#define RTL8366RB_VLAN_UNTAG_MASK 0xff
163#define RTL8366RB_VLAN_MEMBER_MASK 0xff
164#define RTL8366RB_VLAN_FID_MASK 0x7
165
166static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
167    { 0, 0, 4, "IfInOctets" },
168    { 0, 4, 4, "EtherStatsOctets" },
169    { 0, 8, 2, "EtherStatsUnderSizePkts" },
170    { 0, 10, 2, "EtherFragments" },
171    { 0, 12, 2, "EtherStatsPkts64Octets" },
172    { 0, 14, 2, "EtherStatsPkts65to127Octets" },
173    { 0, 16, 2, "EtherStatsPkts128to255Octets" },
174    { 0, 18, 2, "EtherStatsPkts256to511Octets" },
175    { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
176    { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
177    { 0, 24, 2, "EtherOversizeStats" },
178    { 0, 26, 2, "EtherStatsJabbers" },
179    { 0, 28, 2, "IfInUcastPkts" },
180    { 0, 30, 2, "EtherStatsMulticastPkts" },
181    { 0, 32, 2, "EtherStatsBroadcastPkts" },
182    { 0, 34, 2, "EtherStatsDropEvents" },
183    { 0, 36, 2, "Dot3StatsFCSErrors" },
184    { 0, 38, 2, "Dot3StatsSymbolErrors" },
185    { 0, 40, 2, "Dot3InPauseFrames" },
186    { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
187    { 0, 44, 4, "IfOutOctets" },
188    { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
189    { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
190    { 0, 52, 2, "Dot3sDeferredTransmissions" },
191    { 0, 54, 2, "Dot3StatsLateCollisions" },
192    { 0, 56, 2, "EtherStatsCollisions" },
193    { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
194    { 0, 60, 2, "Dot3OutPauseFrames" },
195    { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
196    { 0, 64, 2, "Dot1dTpPortInDiscards" },
197    { 0, 66, 2, "IfOutUcastPkts" },
198    { 0, 68, 2, "IfOutMulticastPkts" },
199    { 0, 70, 2, "IfOutBroadcastPkts" },
200};
201
202#define REG_WR(_smi, _reg, _val) \
203    do { \
204        err = rtl8366_smi_write_reg(_smi, _reg, _val); \
205        if (err) \
206            return err; \
207    } while (0)
208
209#define REG_RMW(_smi, _reg, _mask, _val) \
210    do { \
211        err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
212        if (err) \
213            return err; \
214    } while (0)
215
216static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
217{
218    int timeout = 10;
219    u32 data;
220
221    rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
222                  RTL8366RB_CHIP_CTRL_RESET_HW);
223    do {
224        msleep(1);
225        if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
226            return -EIO;
227
228        if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
229            break;
230    } while (--timeout);
231
232    if (!timeout) {
233        printk("Timeout waiting for the switch to reset\n");
234        return -EIO;
235    }
236
237    return 0;
238}
239
240static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
241{
242    int err;
243
244    /* set maximum packet length to 1536 bytes */
245    REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
246        RTL8366RB_SGCR_MAX_LENGTH_1536);
247
248    /* enable all ports */
249    REG_WR(smi, RTL8366RB_PECR, 0);
250
251    /* enable learning for all ports */
252    REG_WR(smi, RTL8366RB_SSCR0, 0);
253
254    /* enable auto ageing for all ports */
255    REG_WR(smi, RTL8366RB_SSCR1, 0);
256
257    /*
258     * discard VLAN tagged packets if the port is not a member of
259     * the VLAN with which the packets is associated.
260     */
261    REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
262
263    /* don't drop packets whose DA has not been learned */
264    REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
265
266    return 0;
267}
268
269static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
270                 u32 phy_no, u32 page, u32 addr, u32 *data)
271{
272    u32 reg;
273    int ret;
274
275    if (phy_no > RTL8366RB_PHY_NO_MAX)
276        return -EINVAL;
277
278    if (page > RTL8366RB_PHY_PAGE_MAX)
279        return -EINVAL;
280
281    if (addr > RTL8366RB_PHY_ADDR_MAX)
282        return -EINVAL;
283
284    ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
285                    RTL8366RB_PHY_CTRL_READ);
286    if (ret)
287        return ret;
288
289    reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
290          ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
291          (addr & RTL8366RB_PHY_REG_MASK);
292
293    ret = rtl8366_smi_write_reg(smi, reg, 0);
294    if (ret)
295        return ret;
296
297    ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
298    if (ret)
299        return ret;
300
301    return 0;
302}
303
304static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
305                  u32 phy_no, u32 page, u32 addr, u32 data)
306{
307    u32 reg;
308    int ret;
309
310    if (phy_no > RTL8366RB_PHY_NO_MAX)
311        return -EINVAL;
312
313    if (page > RTL8366RB_PHY_PAGE_MAX)
314        return -EINVAL;
315
316    if (addr > RTL8366RB_PHY_ADDR_MAX)
317        return -EINVAL;
318
319    ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
320                    RTL8366RB_PHY_CTRL_WRITE);
321    if (ret)
322        return ret;
323
324    reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
325          ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
326          (addr & RTL8366RB_PHY_REG_MASK);
327
328    ret = rtl8366_smi_write_reg(smi, reg, data);
329    if (ret)
330        return ret;
331
332    return 0;
333}
334
335static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
336                     int port, unsigned long long *val)
337{
338    int i;
339    int err;
340    u32 addr, data;
341    u64 mibvalue;
342
343    if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
344        return -EINVAL;
345
346    addr = RTL8366RB_MIB_COUNTER_BASE +
347           RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
348           rtl8366rb_mib_counters[counter].offset;
349
350    /*
351     * Writing access counter address first
352     * then ASIC will prepare 64bits counter wait for being retrived
353     */
354    data = 0; /* writing data will be discard by ASIC */
355    err = rtl8366_smi_write_reg(smi, addr, data);
356    if (err)
357        return err;
358
359    /* read MIB control register */
360    err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
361    if (err)
362        return err;
363
364    if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
365        return -EBUSY;
366
367    if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
368        return -EIO;
369
370    mibvalue = 0;
371    for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
372        err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
373        if (err)
374            return err;
375
376        mibvalue = (mibvalue << 16) | (data & 0xFFFF);
377    }
378
379    *val = mibvalue;
380    return 0;
381}
382
383static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
384                 struct rtl8366_vlan_4k *vlan4k)
385{
386    u32 data[3];
387    int err;
388    int i;
389
390    memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
391
392    if (vid >= RTL8366RB_NUM_VIDS)
393        return -EINVAL;
394
395    /* write VID */
396    err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
397                    vid & RTL8366RB_VLAN_VID_MASK);
398    if (err)
399        return err;
400
401    /* write table access control word */
402    err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
403                    RTL8366RB_TABLE_VLAN_READ_CTRL);
404    if (err)
405        return err;
406
407    for (i = 0; i < 3; i++) {
408        err = rtl8366_smi_read_reg(smi,
409                       RTL8366RB_VLAN_TABLE_READ_BASE + i,
410                       &data[i]);
411        if (err)
412            return err;
413    }
414
415    vlan4k->vid = vid;
416    vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
417            RTL8366RB_VLAN_UNTAG_MASK;
418    vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
419    vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
420
421    return 0;
422}
423
424static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
425                 const struct rtl8366_vlan_4k *vlan4k)
426{
427    u32 data[3];
428    int err;
429    int i;
430
431    if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
432        vlan4k->member > RTL8366RB_PORT_ALL ||
433        vlan4k->untag > RTL8366RB_PORT_ALL ||
434        vlan4k->fid > RTL8366RB_FIDMAX)
435        return -EINVAL;
436
437    data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
438    data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
439          ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
440            RTL8366RB_VLAN_UNTAG_SHIFT);
441    data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
442
443    for (i = 0; i < 3; i++) {
444        err = rtl8366_smi_write_reg(smi,
445                        RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
446                        data[i]);
447        if (err)
448            return err;
449    }
450
451    /* write table access control word */
452    err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
453                    RTL8366RB_TABLE_VLAN_WRITE_CTRL);
454
455    return err;
456}
457
458static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
459                 struct rtl8366_vlan_mc *vlanmc)
460{
461    u32 data[3];
462    int err;
463    int i;
464
465    memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
466
467    if (index >= RTL8366RB_NUM_VLANS)
468        return -EINVAL;
469
470    for (i = 0; i < 3; i++) {
471        err = rtl8366_smi_read_reg(smi,
472                       RTL8366RB_VLAN_MC_BASE(index) + i,
473                       &data[i]);
474        if (err)
475            return err;
476    }
477
478    vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
479    vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
480               RTL8366RB_VLAN_PRIORITY_MASK;
481    vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
482            RTL8366RB_VLAN_UNTAG_MASK;
483    vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
484    vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
485
486    return 0;
487}
488
489static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
490                 const struct rtl8366_vlan_mc *vlanmc)
491{
492    u32 data[3];
493    int err;
494    int i;
495
496    if (index >= RTL8366RB_NUM_VLANS ||
497        vlanmc->vid >= RTL8366RB_NUM_VIDS ||
498        vlanmc->priority > RTL8366RB_PRIORITYMAX ||
499        vlanmc->member > RTL8366RB_PORT_ALL ||
500        vlanmc->untag > RTL8366RB_PORT_ALL ||
501        vlanmc->fid > RTL8366RB_FIDMAX)
502        return -EINVAL;
503
504    data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
505          ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
506            RTL8366RB_VLAN_PRIORITY_SHIFT);
507    data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
508          ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
509            RTL8366RB_VLAN_UNTAG_SHIFT);
510    data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
511
512    for (i = 0; i < 3; i++) {
513        err = rtl8366_smi_write_reg(smi,
514                        RTL8366RB_VLAN_MC_BASE(index) + i,
515                        data[i]);
516        if (err)
517            return err;
518    }
519
520    return 0;
521}
522
523static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
524{
525    u32 data;
526    int err;
527
528    if (port >= RTL8366RB_NUM_PORTS)
529        return -EINVAL;
530
531    err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
532                   &data);
533    if (err)
534        return err;
535
536    *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
537           RTL8366RB_PORT_VLAN_CTRL_MASK;
538
539    return 0;
540
541}
542
543static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
544{
545    if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
546        return -EINVAL;
547
548    return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
549                RTL8366RB_PORT_VLAN_CTRL_MASK <<
550                    RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
551                (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
552                    RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
553}
554
555static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
556{
557    unsigned max = RTL8366RB_NUM_VLANS;
558
559    if (smi->vlan4k_enabled)
560        max = RTL8366RB_NUM_VIDS - 1;
561
562    if (vlan == 0 || vlan >= max)
563        return 0;
564
565    return 1;
566}
567
568static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
569{
570    return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
571                (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
572}
573
574static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
575{
576    return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
577                RTL8366RB_SGCR_EN_VLAN_4KTB,
578                (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
579}
580
581static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
582                  const struct switch_attr *attr,
583                  struct switch_val *val)
584{
585    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
586
587    return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
588                    RTL8366RB_MIB_CTRL_GLOBAL_RESET);
589}
590
591static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
592                     const struct switch_attr *attr,
593                     struct switch_val *val)
594{
595    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
596    u32 data;
597
598    rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
599
600    val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
601
602    return 0;
603}
604
605static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
606                    const struct switch_attr *attr,
607                    struct switch_val *val)
608{
609    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
610
611    if (val->value.i >= 6)
612        return -EINVAL;
613
614    return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
615                RTL8366RB_LED_BLINKRATE_MASK,
616                val->value.i);
617}
618
619static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
620                       const struct switch_attr *attr,
621                       struct switch_val *val)
622{
623    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
624    u32 data;
625
626    rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
627    val->value.i = !data;
628
629    return 0;
630}
631
632
633static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
634                       const struct switch_attr *attr,
635                       struct switch_val *val)
636{
637    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
638    u32 portmask = 0;
639    int err = 0;
640
641    if (!val->value.i)
642        portmask = RTL8366RB_PORT_ALL;
643
644    /* set learning for all ports */
645    REG_WR(smi, RTL8366RB_SSCR0, portmask);
646
647    /* set auto ageing for all ports */
648    REG_WR(smi, RTL8366RB_SSCR1, portmask);
649
650    return 0;
651}
652
653
654static const char *rtl8366rb_speed_str(unsigned speed)
655{
656    switch (speed) {
657    case 0:
658        return "10baseT";
659    case 1:
660        return "100baseT";
661    case 2:
662        return "1000baseT";
663    }
664
665    return "unknown";
666}
667
668static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
669                     const struct switch_attr *attr,
670                     struct switch_val *val)
671{
672    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
673    u32 len = 0, data = 0;
674
675    if (val->port_vlan >= RTL8366RB_NUM_PORTS)
676        return -EINVAL;
677
678    memset(smi->buf, '\0', sizeof(smi->buf));
679    rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
680                 (val->port_vlan / 2), &data);
681
682    if (val->port_vlan % 2)
683        data = data >> 8;
684
685    if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
686        len = snprintf(smi->buf, sizeof(smi->buf),
687                "port:%d link:up speed:%s %s-duplex %s%s%s",
688                val->port_vlan,
689                rtl8366rb_speed_str(data &
690                      RTL8366RB_PORT_STATUS_SPEED_MASK),
691                (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
692                    "full" : "half",
693                (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
694                    "tx-pause ": "",
695                (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
696                    "rx-pause " : "",
697                (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
698                    "nway ": "");
699    } else {
700        len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
701                val->port_vlan);
702    }
703
704    val->value.s = smi->buf;
705    val->len = len;
706
707    return 0;
708}
709
710static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
711                    const struct switch_attr *attr,
712                    struct switch_val *val)
713{
714    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
715    u32 data;
716    u32 mask;
717    u32 reg;
718
719    if (val->port_vlan >= RTL8366RB_NUM_PORTS)
720        return -EINVAL;
721
722    if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
723        reg = RTL8366RB_LED_BLINKRATE_REG;
724        mask = 0xF << 4;
725        data = val->value.i << 4;
726    } else {
727        reg = RTL8366RB_LED_CTRL_REG;
728        mask = 0xF << (val->port_vlan * 4),
729        data = val->value.i << (val->port_vlan * 4);
730    }
731
732    return rtl8366_smi_rmwr(smi, reg, mask, data);
733}
734
735static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
736                    const struct switch_attr *attr,
737                    struct switch_val *val)
738{
739    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
740    u32 data = 0;
741
742    if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
743        return -EINVAL;
744
745    rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
746    val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
747
748    return 0;
749}
750
751static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
752                       const struct switch_attr *attr,
753                       struct switch_val *val)
754{
755    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
756
757    if (val->port_vlan >= RTL8366RB_NUM_PORTS)
758        return -EINVAL;
759
760    return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
761                RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
762}
763
764static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
765{
766    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
767    int err;
768
769    err = rtl8366rb_reset_chip(smi);
770    if (err)
771        return err;
772
773    err = rtl8366rb_hw_init(smi);
774    if (err)
775        return err;
776
777    return rtl8366_reset_vlan(smi);
778}
779
780static struct switch_attr rtl8366rb_globals[] = {
781    {
782        .type = SWITCH_TYPE_INT,
783        .name = "enable_learning",
784        .description = "Enable learning, enable aging",
785        .set = rtl8366rb_sw_set_learning_enable,
786        .get = rtl8366rb_sw_get_learning_enable,
787        .max = 1
788    }, {
789        .type = SWITCH_TYPE_INT,
790        .name = "enable_vlan",
791        .description = "Enable VLAN mode",
792        .set = rtl8366_sw_set_vlan_enable,
793        .get = rtl8366_sw_get_vlan_enable,
794        .max = 1,
795        .ofs = 1
796    }, {
797        .type = SWITCH_TYPE_INT,
798        .name = "enable_vlan4k",
799        .description = "Enable VLAN 4K mode",
800        .set = rtl8366_sw_set_vlan_enable,
801        .get = rtl8366_sw_get_vlan_enable,
802        .max = 1,
803        .ofs = 2
804    }, {
805        .type = SWITCH_TYPE_NOVAL,
806        .name = "reset_mibs",
807        .description = "Reset all MIB counters",
808        .set = rtl8366rb_sw_reset_mibs,
809    }, {
810        .type = SWITCH_TYPE_INT,
811        .name = "blinkrate",
812        .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
813        " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
814        .set = rtl8366rb_sw_set_blinkrate,
815        .get = rtl8366rb_sw_get_blinkrate,
816        .max = 5
817    },
818};
819
820static struct switch_attr rtl8366rb_port[] = {
821    {
822        .type = SWITCH_TYPE_STRING,
823        .name = "link",
824        .description = "Get port link information",
825        .max = 1,
826        .set = NULL,
827        .get = rtl8366rb_sw_get_port_link,
828    }, {
829        .type = SWITCH_TYPE_NOVAL,
830        .name = "reset_mib",
831        .description = "Reset single port MIB counters",
832        .set = rtl8366rb_sw_reset_port_mibs,
833    }, {
834        .type = SWITCH_TYPE_STRING,
835        .name = "mib",
836        .description = "Get MIB counters for port",
837        .max = 33,
838        .set = NULL,
839        .get = rtl8366_sw_get_port_mib,
840    }, {
841        .type = SWITCH_TYPE_INT,
842        .name = "led",
843        .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
844        .max = 15,
845        .set = rtl8366rb_sw_set_port_led,
846        .get = rtl8366rb_sw_get_port_led,
847    },
848};
849
850static struct switch_attr rtl8366rb_vlan[] = {
851    {
852        .type = SWITCH_TYPE_STRING,
853        .name = "info",
854        .description = "Get vlan information",
855        .max = 1,
856        .set = NULL,
857        .get = rtl8366_sw_get_vlan_info,
858    },
859};
860
861static const struct switch_dev_ops rtl8366_ops = {
862    .attr_global = {
863        .attr = rtl8366rb_globals,
864        .n_attr = ARRAY_SIZE(rtl8366rb_globals),
865    },
866    .attr_port = {
867        .attr = rtl8366rb_port,
868        .n_attr = ARRAY_SIZE(rtl8366rb_port),
869    },
870    .attr_vlan = {
871        .attr = rtl8366rb_vlan,
872        .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
873    },
874
875    .get_vlan_ports = rtl8366_sw_get_vlan_ports,
876    .set_vlan_ports = rtl8366_sw_set_vlan_ports,
877    .get_port_pvid = rtl8366_sw_get_port_pvid,
878    .set_port_pvid = rtl8366_sw_set_port_pvid,
879    .reset_switch = rtl8366rb_sw_reset_switch,
880};
881
882static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
883{
884    struct switch_dev *dev = &smi->sw_dev;
885    int err;
886
887    dev->name = "RTL8366RB";
888    dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
889    dev->ports = RTL8366RB_NUM_PORTS;
890    dev->vlans = RTL8366RB_NUM_VIDS;
891    dev->ops = &rtl8366_ops;
892    dev->devname = dev_name(smi->parent);
893
894    err = register_switch(dev, NULL);
895    if (err)
896        dev_err(smi->parent, "switch registration failed\n");
897
898    return err;
899}
900
901static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
902{
903    unregister_switch(&smi->sw_dev);
904}
905
906static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
907{
908    struct rtl8366_smi *smi = bus->priv;
909    u32 val = 0;
910    int err;
911
912    err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
913    if (err)
914        return 0xffff;
915
916    return val;
917}
918
919static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
920{
921    struct rtl8366_smi *smi = bus->priv;
922    u32 t;
923    int err;
924
925    err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
926    /* flush write */
927    (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
928
929    return err;
930}
931
932static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
933{
934    return (bus->read == rtl8366rb_mii_read &&
935        bus->write == rtl8366rb_mii_write);
936}
937
938static int rtl8366rb_setup(struct rtl8366_smi *smi)
939{
940    int ret;
941
942    ret = rtl8366rb_reset_chip(smi);
943    if (ret)
944        return ret;
945
946    ret = rtl8366rb_hw_init(smi);
947    return ret;
948}
949
950static int rtl8366rb_detect(struct rtl8366_smi *smi)
951{
952    u32 chip_id = 0;
953    u32 chip_ver = 0;
954    int ret;
955
956    ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
957    if (ret) {
958        dev_err(smi->parent, "unable to read chip id\n");
959        return ret;
960    }
961
962    switch (chip_id) {
963    case RTL8366RB_CHIP_ID_8366:
964        break;
965    default:
966        dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
967        return -ENODEV;
968    }
969
970    ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
971                   &chip_ver);
972    if (ret) {
973        dev_err(smi->parent, "unable to read chip version\n");
974        return ret;
975    }
976
977    dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
978         chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
979
980    return 0;
981}
982
983static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
984    .detect = rtl8366rb_detect,
985    .setup = rtl8366rb_setup,
986
987    .mii_read = rtl8366rb_mii_read,
988    .mii_write = rtl8366rb_mii_write,
989
990    .get_vlan_mc = rtl8366rb_get_vlan_mc,
991    .set_vlan_mc = rtl8366rb_set_vlan_mc,
992    .get_vlan_4k = rtl8366rb_get_vlan_4k,
993    .set_vlan_4k = rtl8366rb_set_vlan_4k,
994    .get_mc_index = rtl8366rb_get_mc_index,
995    .set_mc_index = rtl8366rb_set_mc_index,
996    .get_mib_counter = rtl8366rb_get_mib_counter,
997    .is_vlan_valid = rtl8366rb_is_vlan_valid,
998    .enable_vlan = rtl8366rb_enable_vlan,
999    .enable_vlan4k = rtl8366rb_enable_vlan4k,
1000};
1001
1002static int __init rtl8366rb_probe(struct platform_device *pdev)
1003{
1004    static int rtl8366_smi_version_printed;
1005    struct rtl8366rb_platform_data *pdata;
1006    struct rtl8366_smi *smi;
1007    int err;
1008
1009    if (!rtl8366_smi_version_printed++)
1010        printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1011               " version " RTL8366RB_DRIVER_VER"\n");
1012
1013    pdata = pdev->dev.platform_data;
1014    if (!pdata) {
1015        dev_err(&pdev->dev, "no platform data specified\n");
1016        err = -EINVAL;
1017        goto err_out;
1018    }
1019
1020    smi = rtl8366_smi_alloc(&pdev->dev);
1021    if (!smi) {
1022        err = -ENOMEM;
1023        goto err_out;
1024    }
1025
1026    smi->gpio_sda = pdata->gpio_sda;
1027    smi->gpio_sck = pdata->gpio_sck;
1028    smi->ops = &rtl8366rb_smi_ops;
1029    smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1030    smi->num_ports = RTL8366RB_NUM_PORTS;
1031    smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1032    smi->mib_counters = rtl8366rb_mib_counters;
1033    smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1034
1035    err = rtl8366_smi_init(smi);
1036    if (err)
1037        goto err_free_smi;
1038
1039    platform_set_drvdata(pdev, smi);
1040
1041    err = rtl8366rb_switch_init(smi);
1042    if (err)
1043        goto err_clear_drvdata;
1044
1045    return 0;
1046
1047 err_clear_drvdata:
1048    platform_set_drvdata(pdev, NULL);
1049    rtl8366_smi_cleanup(smi);
1050 err_free_smi:
1051    kfree(smi);
1052 err_out:
1053    return err;
1054}
1055
1056static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1057{
1058    if (!rtl8366rb_mii_bus_match(phydev->bus))
1059        return -EINVAL;
1060
1061    return 0;
1062}
1063
1064static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1065{
1066    return 0;
1067}
1068
1069static struct phy_driver rtl8366rb_phy_driver = {
1070    .phy_id = 0x001cc960,
1071    .name = "Realtek RTL8366RB",
1072    .phy_id_mask = 0x1ffffff0,
1073    .features = PHY_GBIT_FEATURES,
1074    .config_aneg = rtl8366rb_phy_config_aneg,
1075    .config_init = rtl8366rb_phy_config_init,
1076    .read_status = genphy_read_status,
1077    .driver = {
1078        .owner = THIS_MODULE,
1079    },
1080};
1081
1082static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1083{
1084    struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1085
1086    if (smi) {
1087        rtl8366rb_switch_cleanup(smi);
1088        platform_set_drvdata(pdev, NULL);
1089        rtl8366_smi_cleanup(smi);
1090        kfree(smi);
1091    }
1092
1093    return 0;
1094}
1095
1096static struct platform_driver rtl8366rb_driver = {
1097    .driver = {
1098        .name = RTL8366RB_DRIVER_NAME,
1099        .owner = THIS_MODULE,
1100    },
1101    .probe = rtl8366rb_probe,
1102    .remove = __devexit_p(rtl8366rb_remove),
1103};
1104
1105static int __init rtl8366rb_module_init(void)
1106{
1107    int ret;
1108    ret = platform_driver_register(&rtl8366rb_driver);
1109    if (ret)
1110        return ret;
1111
1112    ret = phy_driver_register(&rtl8366rb_phy_driver);
1113    if (ret)
1114        goto err_platform_unregister;
1115
1116    return 0;
1117
1118 err_platform_unregister:
1119    platform_driver_unregister(&rtl8366rb_driver);
1120    return ret;
1121}
1122module_init(rtl8366rb_module_init);
1123
1124static void __exit rtl8366rb_module_exit(void)
1125{
1126    phy_driver_unregister(&rtl8366rb_phy_driver);
1127    platform_driver_unregister(&rtl8366rb_driver);
1128}
1129module_exit(rtl8366rb_module_exit);
1130
1131MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1132MODULE_VERSION(RTL8366RB_DRIVER_VER);
1133MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1134MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1135MODULE_LICENSE("GPL v2");
1136MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
1137

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