Root/target/linux/generic-2.6/files/drivers/net/phy/rtl8366s.c

1/*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/skbuff.h>
18#include <linux/rtl8366s.h>
19
20#include "rtl8366_smi.h"
21
22#define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
23#define RTL8366S_DRIVER_VER "0.2.2"
24
25#define RTL8366S_PHY_NO_MAX 4
26#define RTL8366S_PHY_PAGE_MAX 7
27#define RTL8366S_PHY_ADDR_MAX 31
28
29/* Switch Global Configuration register */
30#define RTL8366S_SGCR 0x0000
31#define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
32#define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
33#define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
34#define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
35#define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
36#define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
37#define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
38#define RTL8366S_SGCR_EN_VLAN BIT(13)
39
40/* Port Enable Control register */
41#define RTL8366S_PECR 0x0001
42
43/* Switch Security Control registers */
44#define RTL8366S_SSCR0 0x0002
45#define RTL8366S_SSCR1 0x0003
46#define RTL8366S_SSCR2 0x0004
47#define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
48
49#define RTL8366S_RESET_CTRL_REG 0x0100
50#define RTL8366S_CHIP_CTRL_RESET_HW 1
51#define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
52
53#define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
54#define RTL8366S_CHIP_VERSION_MASK 0xf
55#define RTL8366S_CHIP_ID_REG 0x0105
56#define RTL8366S_CHIP_ID_8366 0x8366
57
58/* PHY registers control */
59#define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
60#define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
61
62#define RTL8366S_PHY_CTRL_READ 1
63#define RTL8366S_PHY_CTRL_WRITE 0
64
65#define RTL8366S_PHY_REG_MASK 0x1f
66#define RTL8366S_PHY_PAGE_OFFSET 5
67#define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
68#define RTL8366S_PHY_NO_OFFSET 9
69#define RTL8366S_PHY_NO_MASK (0x1f << 9)
70
71/* LED control registers */
72#define RTL8366S_LED_BLINKRATE_REG 0x0420
73#define RTL8366S_LED_BLINKRATE_BIT 0
74#define RTL8366S_LED_BLINKRATE_MASK 0x0007
75
76#define RTL8366S_LED_CTRL_REG 0x0421
77#define RTL8366S_LED_0_1_CTRL_REG 0x0422
78#define RTL8366S_LED_2_3_CTRL_REG 0x0423
79
80#define RTL8366S_MIB_COUNT 33
81#define RTL8366S_GLOBAL_MIB_COUNT 1
82#define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
83#define RTL8366S_MIB_COUNTER_BASE 0x1000
84#define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
85#define RTL8366S_MIB_COUNTER_BASE2 0x1180
86#define RTL8366S_MIB_CTRL_REG 0x11F0
87#define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
88#define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
89#define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
90
91#define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
92#define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
93#define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
94
95
96#define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
97#define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
98        (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
99#define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
100#define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
101
102
103#define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
104#define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
105
106#define RTL8366S_VLAN_TB_CTRL_REG 0x010F
107
108#define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
109#define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
110#define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
111
112#define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2)
113
114#define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379
115
116#define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
117#define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
118#define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
119#define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
120#define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
121#define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
122#define RTL8366S_PORT_STATUS_AN_MASK 0x0080
123
124
125#define RTL8366S_PORT_NUM_CPU 5
126#define RTL8366S_NUM_PORTS 6
127#define RTL8366S_NUM_VLANS 16
128#define RTL8366S_NUM_LEDGROUPS 4
129#define RTL8366S_NUM_VIDS 4096
130#define RTL8366S_PRIORITYMAX 7
131#define RTL8366S_FIDMAX 7
132
133
134#define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
135#define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
136#define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
137#define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
138
139#define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
140#define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
141
142#define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
143                     RTL8366S_PORT_2 | \
144                     RTL8366S_PORT_3 | \
145                     RTL8366S_PORT_4 | \
146                     RTL8366S_PORT_UNKNOWN | \
147                     RTL8366S_PORT_CPU)
148
149#define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
150                     RTL8366S_PORT_2 | \
151                     RTL8366S_PORT_3 | \
152                     RTL8366S_PORT_4 | \
153                     RTL8366S_PORT_UNKNOWN)
154
155#define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
156                     RTL8366S_PORT_2 | \
157                     RTL8366S_PORT_3 | \
158                     RTL8366S_PORT_4)
159
160#define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
161                     RTL8366S_PORT_CPU)
162
163#define RTL8366S_VLAN_VID_MASK 0xfff
164#define RTL8366S_VLAN_PRIORITY_SHIFT 12
165#define RTL8366S_VLAN_PRIORITY_MASK 0x7
166#define RTL8366S_VLAN_MEMBER_MASK 0x3f
167#define RTL8366S_VLAN_UNTAG_SHIFT 6
168#define RTL8366S_VLAN_UNTAG_MASK 0x3f
169#define RTL8366S_VLAN_FID_SHIFT 12
170#define RTL8366S_VLAN_FID_MASK 0x7
171
172static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
173    { 0, 0, 4, "IfInOctets" },
174    { 0, 4, 4, "EtherStatsOctets" },
175    { 0, 8, 2, "EtherStatsUnderSizePkts" },
176    { 0, 10, 2, "EtherFragments" },
177    { 0, 12, 2, "EtherStatsPkts64Octets" },
178    { 0, 14, 2, "EtherStatsPkts65to127Octets" },
179    { 0, 16, 2, "EtherStatsPkts128to255Octets" },
180    { 0, 18, 2, "EtherStatsPkts256to511Octets" },
181    { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
182    { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
183    { 0, 24, 2, "EtherOversizeStats" },
184    { 0, 26, 2, "EtherStatsJabbers" },
185    { 0, 28, 2, "IfInUcastPkts" },
186    { 0, 30, 2, "EtherStatsMulticastPkts" },
187    { 0, 32, 2, "EtherStatsBroadcastPkts" },
188    { 0, 34, 2, "EtherStatsDropEvents" },
189    { 0, 36, 2, "Dot3StatsFCSErrors" },
190    { 0, 38, 2, "Dot3StatsSymbolErrors" },
191    { 0, 40, 2, "Dot3InPauseFrames" },
192    { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
193    { 0, 44, 4, "IfOutOctets" },
194    { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
195    { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
196    { 0, 52, 2, "Dot3sDeferredTransmissions" },
197    { 0, 54, 2, "Dot3StatsLateCollisions" },
198    { 0, 56, 2, "EtherStatsCollisions" },
199    { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
200    { 0, 60, 2, "Dot3OutPauseFrames" },
201    { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
202
203    /*
204     * The following counters are accessible at a different
205     * base address.
206     */
207    { 1, 0, 2, "Dot1dTpPortInDiscards" },
208    { 1, 2, 2, "IfOutUcastPkts" },
209    { 1, 4, 2, "IfOutMulticastPkts" },
210    { 1, 6, 2, "IfOutBroadcastPkts" },
211};
212
213#define REG_WR(_smi, _reg, _val) \
214    do { \
215        err = rtl8366_smi_write_reg(_smi, _reg, _val); \
216        if (err) \
217            return err; \
218    } while (0)
219
220#define REG_RMW(_smi, _reg, _mask, _val) \
221    do { \
222        err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
223        if (err) \
224            return err; \
225    } while (0)
226
227static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
228{
229    int timeout = 10;
230    u32 data;
231
232    rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
233                  RTL8366S_CHIP_CTRL_RESET_HW);
234    do {
235        msleep(1);
236        if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
237            return -EIO;
238
239        if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
240            break;
241    } while (--timeout);
242
243    if (!timeout) {
244        printk("Timeout waiting for the switch to reset\n");
245        return -EIO;
246    }
247
248    return 0;
249}
250
251static int rtl8366s_hw_init(struct rtl8366_smi *smi)
252{
253    int err;
254
255    /* set maximum packet length to 1536 bytes */
256    REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
257        RTL8366S_SGCR_MAX_LENGTH_1536);
258
259    /* enable all ports */
260    REG_WR(smi, RTL8366S_PECR, 0);
261
262    /* enable learning for all ports */
263    REG_WR(smi, RTL8366S_SSCR0, 0);
264
265    /* enable auto ageing for all ports */
266    REG_WR(smi, RTL8366S_SSCR1, 0);
267
268    /*
269     * discard VLAN tagged packets if the port is not a member of
270     * the VLAN with which the packets is associated.
271     */
272    REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
273
274    /* don't drop packets whose DA has not been learned */
275    REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
276
277    return 0;
278}
279
280static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
281                 u32 phy_no, u32 page, u32 addr, u32 *data)
282{
283    u32 reg;
284    int ret;
285
286    if (phy_no > RTL8366S_PHY_NO_MAX)
287        return -EINVAL;
288
289    if (page > RTL8366S_PHY_PAGE_MAX)
290        return -EINVAL;
291
292    if (addr > RTL8366S_PHY_ADDR_MAX)
293        return -EINVAL;
294
295    ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
296                    RTL8366S_PHY_CTRL_READ);
297    if (ret)
298        return ret;
299
300    reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
301          ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
302          (addr & RTL8366S_PHY_REG_MASK);
303
304    ret = rtl8366_smi_write_reg(smi, reg, 0);
305    if (ret)
306        return ret;
307
308    ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
309    if (ret)
310        return ret;
311
312    return 0;
313}
314
315static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
316                  u32 phy_no, u32 page, u32 addr, u32 data)
317{
318    u32 reg;
319    int ret;
320
321    if (phy_no > RTL8366S_PHY_NO_MAX)
322        return -EINVAL;
323
324    if (page > RTL8366S_PHY_PAGE_MAX)
325        return -EINVAL;
326
327    if (addr > RTL8366S_PHY_ADDR_MAX)
328        return -EINVAL;
329
330    ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
331                    RTL8366S_PHY_CTRL_WRITE);
332    if (ret)
333        return ret;
334
335    reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
336          ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
337          (addr & RTL8366S_PHY_REG_MASK);
338
339    ret = rtl8366_smi_write_reg(smi, reg, data);
340    if (ret)
341        return ret;
342
343    return 0;
344}
345
346static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
347                   int port, unsigned long long *val)
348{
349    int i;
350    int err;
351    u32 addr, data;
352    u64 mibvalue;
353
354    if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
355        return -EINVAL;
356
357    switch (rtl8366s_mib_counters[counter].base) {
358    case 0:
359        addr = RTL8366S_MIB_COUNTER_BASE +
360               RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
361        break;
362
363    case 1:
364        addr = RTL8366S_MIB_COUNTER_BASE2 +
365            RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
366        break;
367
368    default:
369        return -EINVAL;
370    }
371
372    addr += rtl8366s_mib_counters[counter].offset;
373
374    /*
375     * Writing access counter address first
376     * then ASIC will prepare 64bits counter wait for being retrived
377     */
378    data = 0; /* writing data will be discard by ASIC */
379    err = rtl8366_smi_write_reg(smi, addr, data);
380    if (err)
381        return err;
382
383    /* read MIB control register */
384    err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
385    if (err)
386        return err;
387
388    if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
389        return -EBUSY;
390
391    if (data & RTL8366S_MIB_CTRL_RESET_MASK)
392        return -EIO;
393
394    mibvalue = 0;
395    for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
396        err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
397        if (err)
398            return err;
399
400        mibvalue = (mibvalue << 16) | (data & 0xFFFF);
401    }
402
403    *val = mibvalue;
404    return 0;
405}
406
407static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
408                struct rtl8366_vlan_4k *vlan4k)
409{
410    u32 data[2];
411    int err;
412    int i;
413
414    memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
415
416    if (vid >= RTL8366S_NUM_VIDS)
417        return -EINVAL;
418
419    /* write VID */
420    err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
421                    vid & RTL8366S_VLAN_VID_MASK);
422    if (err)
423        return err;
424
425    /* write table access control word */
426    err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
427                    RTL8366S_TABLE_VLAN_READ_CTRL);
428    if (err)
429        return err;
430
431    for (i = 0; i < 2; i++) {
432        err = rtl8366_smi_read_reg(smi,
433                       RTL8366S_VLAN_TABLE_READ_BASE + i,
434                       &data[i]);
435        if (err)
436            return err;
437    }
438
439    vlan4k->vid = vid;
440    vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
441            RTL8366S_VLAN_UNTAG_MASK;
442    vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
443    vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
444            RTL8366S_VLAN_FID_MASK;
445
446    return 0;
447}
448
449static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
450                const struct rtl8366_vlan_4k *vlan4k)
451{
452    u32 data[2];
453    int err;
454    int i;
455
456    if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
457        vlan4k->member > RTL8366S_PORT_ALL ||
458        vlan4k->untag > RTL8366S_PORT_ALL ||
459        vlan4k->fid > RTL8366S_FIDMAX)
460        return -EINVAL;
461
462    data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
463    data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
464          ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
465            RTL8366S_VLAN_UNTAG_SHIFT) |
466          ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
467            RTL8366S_VLAN_FID_SHIFT);
468
469    for (i = 0; i < 2; i++) {
470        err = rtl8366_smi_write_reg(smi,
471                        RTL8366S_VLAN_TABLE_WRITE_BASE + i,
472                        data[i]);
473        if (err)
474            return err;
475    }
476
477    /* write table access control word */
478    err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
479                    RTL8366S_TABLE_VLAN_WRITE_CTRL);
480
481    return err;
482}
483
484static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
485                struct rtl8366_vlan_mc *vlanmc)
486{
487    u32 data[2];
488    int err;
489    int i;
490
491    memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
492
493    if (index >= RTL8366S_NUM_VLANS)
494        return -EINVAL;
495
496    for (i = 0; i < 2; i++) {
497        err = rtl8366_smi_read_reg(smi,
498                       RTL8366S_VLAN_MC_BASE(index) + i,
499                       &data[i]);
500        if (err)
501            return err;
502    }
503
504    vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
505    vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
506               RTL8366S_VLAN_PRIORITY_MASK;
507    vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
508            RTL8366S_VLAN_UNTAG_MASK;
509    vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
510    vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
511              RTL8366S_VLAN_FID_MASK;
512
513    return 0;
514}
515
516static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
517                const struct rtl8366_vlan_mc *vlanmc)
518{
519    u32 data[2];
520    int err;
521    int i;
522
523    if (index >= RTL8366S_NUM_VLANS ||
524        vlanmc->vid >= RTL8366S_NUM_VIDS ||
525        vlanmc->priority > RTL8366S_PRIORITYMAX ||
526        vlanmc->member > RTL8366S_PORT_ALL ||
527        vlanmc->untag > RTL8366S_PORT_ALL ||
528        vlanmc->fid > RTL8366S_FIDMAX)
529        return -EINVAL;
530
531    data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
532          ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
533            RTL8366S_VLAN_PRIORITY_SHIFT);
534    data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
535          ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
536            RTL8366S_VLAN_UNTAG_SHIFT) |
537          ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
538            RTL8366S_VLAN_FID_SHIFT);
539
540    for (i = 0; i < 2; i++) {
541        err = rtl8366_smi_write_reg(smi,
542                        RTL8366S_VLAN_MC_BASE(index) + i,
543                        data[i]);
544        if (err)
545            return err;
546    }
547
548    return 0;
549}
550
551static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
552{
553    u32 data;
554    int err;
555
556    if (port >= RTL8366S_NUM_PORTS)
557        return -EINVAL;
558
559    err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
560                   &data);
561    if (err)
562        return err;
563
564    *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
565           RTL8366S_PORT_VLAN_CTRL_MASK;
566
567    return 0;
568}
569
570static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
571{
572    if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
573        return -EINVAL;
574
575    return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
576                RTL8366S_PORT_VLAN_CTRL_MASK <<
577                    RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
578                (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
579                    RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
580}
581
582static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable)
583{
584    return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
585                (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
586}
587
588static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable)
589{
590    return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
591                1, (enable) ? 1 : 0);
592}
593
594static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
595{
596    unsigned max = RTL8366S_NUM_VLANS;
597
598    if (smi->vlan4k_enabled)
599        max = RTL8366S_NUM_VIDS - 1;
600
601    if (vlan == 0 || vlan >= max)
602        return 0;
603
604    return 1;
605}
606
607static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
608                  const struct switch_attr *attr,
609                  struct switch_val *val)
610{
611    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
612
613    return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
614}
615
616static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
617                     const struct switch_attr *attr,
618                     struct switch_val *val)
619{
620    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
621    u32 data;
622
623    rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
624
625    val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
626
627    return 0;
628}
629
630static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
631                    const struct switch_attr *attr,
632                    struct switch_val *val)
633{
634    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
635
636    if (val->value.i >= 6)
637        return -EINVAL;
638
639    return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
640                RTL8366S_LED_BLINKRATE_MASK,
641                val->value.i);
642}
643
644static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
645                       const struct switch_attr *attr,
646                       struct switch_val *val)
647{
648    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
649    u32 data;
650
651    rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
652    val->value.i = !data;
653
654    return 0;
655}
656
657
658static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
659                       const struct switch_attr *attr,
660                       struct switch_val *val)
661{
662    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
663    u32 portmask = 0;
664    int err = 0;
665
666    if (!val->value.i)
667        portmask = RTL8366S_PORT_ALL;
668
669    /* set learning for all ports */
670    REG_WR(smi, RTL8366S_SSCR0, portmask);
671
672    /* set auto ageing for all ports */
673    REG_WR(smi, RTL8366S_SSCR1, portmask);
674
675    return 0;
676}
677
678
679static const char *rtl8366s_speed_str(unsigned speed)
680{
681    switch (speed) {
682    case 0:
683        return "10baseT";
684    case 1:
685        return "100baseT";
686    case 2:
687        return "1000baseT";
688    }
689
690    return "unknown";
691}
692
693static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
694                     const struct switch_attr *attr,
695                     struct switch_val *val)
696{
697    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
698    u32 len = 0, data = 0;
699
700    if (val->port_vlan >= RTL8366S_NUM_PORTS)
701        return -EINVAL;
702
703    memset(smi->buf, '\0', sizeof(smi->buf));
704    rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
705                 (val->port_vlan / 2), &data);
706
707    if (val->port_vlan % 2)
708        data = data >> 8;
709
710    if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
711        len = snprintf(smi->buf, sizeof(smi->buf),
712                "port:%d link:up speed:%s %s-duplex %s%s%s",
713                val->port_vlan,
714                rtl8366s_speed_str(data &
715                      RTL8366S_PORT_STATUS_SPEED_MASK),
716                (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
717                    "full" : "half",
718                (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
719                    "tx-pause ": "",
720                (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
721                    "rx-pause " : "",
722                (data & RTL8366S_PORT_STATUS_AN_MASK) ?
723                    "nway ": "");
724    } else {
725        len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
726                val->port_vlan);
727    }
728
729    val->value.s = smi->buf;
730    val->len = len;
731
732    return 0;
733}
734
735static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
736                    const struct switch_attr *attr,
737                    struct switch_val *val)
738{
739    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
740    u32 data;
741    u32 mask;
742    u32 reg;
743
744    if (val->port_vlan >= RTL8366S_NUM_PORTS ||
745        (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
746        return -EINVAL;
747
748    if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
749        reg = RTL8366S_LED_BLINKRATE_REG;
750        mask = 0xF << 4;
751        data = val->value.i << 4;
752    } else {
753        reg = RTL8366S_LED_CTRL_REG;
754        mask = 0xF << (val->port_vlan * 4),
755        data = val->value.i << (val->port_vlan * 4);
756    }
757
758    return rtl8366_smi_rmwr(smi, reg, mask, data);
759}
760
761static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
762                    const struct switch_attr *attr,
763                    struct switch_val *val)
764{
765    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
766    u32 data = 0;
767
768    if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
769        return -EINVAL;
770
771    rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
772    val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
773
774    return 0;
775}
776
777static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
778                       const struct switch_attr *attr,
779                       struct switch_val *val)
780{
781    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
782
783    if (val->port_vlan >= RTL8366S_NUM_PORTS)
784        return -EINVAL;
785
786
787    return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
788                0, (1 << (val->port_vlan + 3)));
789}
790
791static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
792{
793    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
794    int err;
795
796    err = rtl8366s_reset_chip(smi);
797    if (err)
798        return err;
799
800    err = rtl8366s_hw_init(smi);
801    if (err)
802        return err;
803
804    return rtl8366_reset_vlan(smi);
805}
806
807static struct switch_attr rtl8366s_globals[] = {
808    {
809        .type = SWITCH_TYPE_INT,
810        .name = "enable_learning",
811        .description = "Enable learning, enable aging",
812        .set = rtl8366s_sw_set_learning_enable,
813        .get = rtl8366s_sw_get_learning_enable,
814        .max = 1,
815    }, {
816        .type = SWITCH_TYPE_INT,
817        .name = "enable_vlan",
818        .description = "Enable VLAN mode",
819        .set = rtl8366_sw_set_vlan_enable,
820        .get = rtl8366_sw_get_vlan_enable,
821        .max = 1,
822        .ofs = 1
823    }, {
824        .type = SWITCH_TYPE_INT,
825        .name = "enable_vlan4k",
826        .description = "Enable VLAN 4K mode",
827        .set = rtl8366_sw_set_vlan_enable,
828        .get = rtl8366_sw_get_vlan_enable,
829        .max = 1,
830        .ofs = 2
831    }, {
832        .type = SWITCH_TYPE_NOVAL,
833        .name = "reset_mibs",
834        .description = "Reset all MIB counters",
835        .set = rtl8366s_sw_reset_mibs,
836    }, {
837        .type = SWITCH_TYPE_INT,
838        .name = "blinkrate",
839        .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
840        " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
841        .set = rtl8366s_sw_set_blinkrate,
842        .get = rtl8366s_sw_get_blinkrate,
843        .max = 5
844    },
845};
846
847static struct switch_attr rtl8366s_port[] = {
848    {
849        .type = SWITCH_TYPE_STRING,
850        .name = "link",
851        .description = "Get port link information",
852        .max = 1,
853        .set = NULL,
854        .get = rtl8366s_sw_get_port_link,
855    }, {
856        .type = SWITCH_TYPE_NOVAL,
857        .name = "reset_mib",
858        .description = "Reset single port MIB counters",
859        .set = rtl8366s_sw_reset_port_mibs,
860    }, {
861        .type = SWITCH_TYPE_STRING,
862        .name = "mib",
863        .description = "Get MIB counters for port",
864        .max = 33,
865        .set = NULL,
866        .get = rtl8366_sw_get_port_mib,
867    }, {
868        .type = SWITCH_TYPE_INT,
869        .name = "led",
870        .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
871        .max = 15,
872        .set = rtl8366s_sw_set_port_led,
873        .get = rtl8366s_sw_get_port_led,
874    },
875};
876
877static struct switch_attr rtl8366s_vlan[] = {
878    {
879        .type = SWITCH_TYPE_STRING,
880        .name = "info",
881        .description = "Get vlan information",
882        .max = 1,
883        .set = NULL,
884        .get = rtl8366_sw_get_vlan_info,
885    },
886};
887
888static const struct switch_dev_ops rtl8366_ops = {
889    .attr_global = {
890        .attr = rtl8366s_globals,
891        .n_attr = ARRAY_SIZE(rtl8366s_globals),
892    },
893    .attr_port = {
894        .attr = rtl8366s_port,
895        .n_attr = ARRAY_SIZE(rtl8366s_port),
896    },
897    .attr_vlan = {
898        .attr = rtl8366s_vlan,
899        .n_attr = ARRAY_SIZE(rtl8366s_vlan),
900    },
901
902    .get_vlan_ports = rtl8366_sw_get_vlan_ports,
903    .set_vlan_ports = rtl8366_sw_set_vlan_ports,
904    .get_port_pvid = rtl8366_sw_get_port_pvid,
905    .set_port_pvid = rtl8366_sw_set_port_pvid,
906    .reset_switch = rtl8366s_sw_reset_switch,
907};
908
909static int rtl8366s_switch_init(struct rtl8366_smi *smi)
910{
911    struct switch_dev *dev = &smi->sw_dev;
912    int err;
913
914    dev->name = "RTL8366S";
915    dev->cpu_port = RTL8366S_PORT_NUM_CPU;
916    dev->ports = RTL8366S_NUM_PORTS;
917    dev->vlans = RTL8366S_NUM_VIDS;
918    dev->ops = &rtl8366_ops;
919    dev->devname = dev_name(smi->parent);
920
921    err = register_switch(dev, NULL);
922    if (err)
923        dev_err(smi->parent, "switch registration failed\n");
924
925    return err;
926}
927
928static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi)
929{
930    unregister_switch(&smi->sw_dev);
931}
932
933static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
934{
935    struct rtl8366_smi *smi = bus->priv;
936    u32 val = 0;
937    int err;
938
939    err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
940    if (err)
941        return 0xffff;
942
943    return val;
944}
945
946static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
947{
948    struct rtl8366_smi *smi = bus->priv;
949    u32 t;
950    int err;
951
952    err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
953    /* flush write */
954    (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
955
956    return err;
957}
958
959static int rtl8366s_mii_bus_match(struct mii_bus *bus)
960{
961    return (bus->read == rtl8366s_mii_read &&
962        bus->write == rtl8366s_mii_write);
963}
964
965static int rtl8366s_setup(struct rtl8366_smi *smi)
966{
967    int ret;
968
969    ret = rtl8366s_reset_chip(smi);
970    if (ret)
971        return ret;
972
973    ret = rtl8366s_hw_init(smi);
974    return ret;
975}
976
977static int rtl8366s_detect(struct rtl8366_smi *smi)
978{
979    u32 chip_id = 0;
980    u32 chip_ver = 0;
981    int ret;
982
983    ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
984    if (ret) {
985        dev_err(smi->parent, "unable to read chip id\n");
986        return ret;
987    }
988
989    switch (chip_id) {
990    case RTL8366S_CHIP_ID_8366:
991        break;
992    default:
993        dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
994        return -ENODEV;
995    }
996
997    ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
998                   &chip_ver);
999    if (ret) {
1000        dev_err(smi->parent, "unable to read chip version\n");
1001        return ret;
1002    }
1003
1004    dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1005         chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1006
1007    return 0;
1008}
1009
1010static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1011    .detect = rtl8366s_detect,
1012    .setup = rtl8366s_setup,
1013
1014    .mii_read = rtl8366s_mii_read,
1015    .mii_write = rtl8366s_mii_write,
1016
1017    .get_vlan_mc = rtl8366s_get_vlan_mc,
1018    .set_vlan_mc = rtl8366s_set_vlan_mc,
1019    .get_vlan_4k = rtl8366s_get_vlan_4k,
1020    .set_vlan_4k = rtl8366s_set_vlan_4k,
1021    .get_mc_index = rtl8366s_get_mc_index,
1022    .set_mc_index = rtl8366s_set_mc_index,
1023    .get_mib_counter = rtl8366_get_mib_counter,
1024    .is_vlan_valid = rtl8366s_is_vlan_valid,
1025    .enable_vlan = rtl8366s_enable_vlan,
1026    .enable_vlan4k = rtl8366s_enable_vlan4k,
1027};
1028
1029static int __init rtl8366s_probe(struct platform_device *pdev)
1030{
1031    static int rtl8366_smi_version_printed;
1032    struct rtl8366s_platform_data *pdata;
1033    struct rtl8366_smi *smi;
1034    int err;
1035
1036    if (!rtl8366_smi_version_printed++)
1037        printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1038               " version " RTL8366S_DRIVER_VER"\n");
1039
1040    pdata = pdev->dev.platform_data;
1041    if (!pdata) {
1042        dev_err(&pdev->dev, "no platform data specified\n");
1043        err = -EINVAL;
1044        goto err_out;
1045    }
1046
1047    smi = rtl8366_smi_alloc(&pdev->dev);
1048    if (!smi) {
1049        err = -ENOMEM;
1050        goto err_out;
1051    }
1052
1053    smi->gpio_sda = pdata->gpio_sda;
1054    smi->gpio_sck = pdata->gpio_sck;
1055    smi->ops = &rtl8366s_smi_ops;
1056    smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1057    smi->num_ports = RTL8366S_NUM_PORTS;
1058    smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1059    smi->mib_counters = rtl8366s_mib_counters;
1060    smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1061
1062    err = rtl8366_smi_init(smi);
1063    if (err)
1064        goto err_free_smi;
1065
1066    platform_set_drvdata(pdev, smi);
1067
1068    err = rtl8366s_switch_init(smi);
1069    if (err)
1070        goto err_clear_drvdata;
1071
1072    return 0;
1073
1074 err_clear_drvdata:
1075    platform_set_drvdata(pdev, NULL);
1076    rtl8366_smi_cleanup(smi);
1077 err_free_smi:
1078    kfree(smi);
1079 err_out:
1080    return err;
1081}
1082
1083static int rtl8366s_phy_config_init(struct phy_device *phydev)
1084{
1085    if (!rtl8366s_mii_bus_match(phydev->bus))
1086        return -EINVAL;
1087
1088    return 0;
1089}
1090
1091static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1092{
1093    return 0;
1094}
1095
1096static struct phy_driver rtl8366s_phy_driver = {
1097    .phy_id = 0x001cc960,
1098    .name = "Realtek RTL8366S",
1099    .phy_id_mask = 0x1ffffff0,
1100    .features = PHY_GBIT_FEATURES,
1101    .config_aneg = rtl8366s_phy_config_aneg,
1102    .config_init = rtl8366s_phy_config_init,
1103    .read_status = genphy_read_status,
1104    .driver = {
1105        .owner = THIS_MODULE,
1106    },
1107};
1108
1109static int __devexit rtl8366s_remove(struct platform_device *pdev)
1110{
1111    struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1112
1113    if (smi) {
1114        rtl8366s_switch_cleanup(smi);
1115        platform_set_drvdata(pdev, NULL);
1116        rtl8366_smi_cleanup(smi);
1117        kfree(smi);
1118    }
1119
1120    return 0;
1121}
1122
1123static struct platform_driver rtl8366s_driver = {
1124    .driver = {
1125        .name = RTL8366S_DRIVER_NAME,
1126        .owner = THIS_MODULE,
1127    },
1128    .probe = rtl8366s_probe,
1129    .remove = __devexit_p(rtl8366s_remove),
1130};
1131
1132static int __init rtl8366s_module_init(void)
1133{
1134    int ret;
1135    ret = platform_driver_register(&rtl8366s_driver);
1136    if (ret)
1137        return ret;
1138
1139    ret = phy_driver_register(&rtl8366s_phy_driver);
1140    if (ret)
1141        goto err_platform_unregister;
1142
1143    return 0;
1144
1145 err_platform_unregister:
1146    platform_driver_unregister(&rtl8366s_driver);
1147    return ret;
1148}
1149module_init(rtl8366s_module_init);
1150
1151static void __exit rtl8366s_module_exit(void)
1152{
1153    phy_driver_unregister(&rtl8366s_phy_driver);
1154    platform_driver_unregister(&rtl8366s_driver);
1155}
1156module_exit(rtl8366s_module_exit);
1157
1158MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1159MODULE_VERSION(RTL8366S_DRIVER_VER);
1160MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1161MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1162MODULE_LICENSE("GPL v2");
1163MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
1164

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