Root/target/linux/generic-2.6/files/drivers/net/phy/rtl8366rb.c

1/*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/skbuff.h>
18#include <linux/rtl8366rb.h>
19
20#include "rtl8366_smi.h"
21
22#define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
23#define RTL8366RB_DRIVER_VER "0.2.2"
24
25#define RTL8366RB_PHY_NO_MAX 4
26#define RTL8366RB_PHY_PAGE_MAX 7
27#define RTL8366RB_PHY_ADDR_MAX 31
28#define RTL8366RB_PHY_WAN 4
29
30/* Switch Global Configuration register */
31#define RTL8366RB_SGCR 0x0000
32#define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
33#define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
34#define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
35#define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
36#define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
37#define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
38#define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
39#define RTL8366RB_SGCR_EN_VLAN BIT(13)
40#define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
41
42/* Port Enable Control register */
43#define RTL8366RB_PECR 0x0001
44
45/* Switch Security Control registers */
46#define RTL8366RB_SSCR0 0x0002
47#define RTL8366RB_SSCR1 0x0003
48#define RTL8366RB_SSCR2 0x0004
49#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
50
51#define RTL8366RB_RESET_CTRL_REG 0x0100
52#define RTL8366RB_CHIP_CTRL_RESET_HW 1
53#define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
54
55#define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
56#define RTL8366RB_CHIP_VERSION_MASK 0xf
57#define RTL8366RB_CHIP_ID_REG 0x0509
58#define RTL8366RB_CHIP_ID_8366 0x5937
59
60/* PHY registers control */
61#define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
62#define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
63
64#define RTL8366RB_PHY_CTRL_READ 1
65#define RTL8366RB_PHY_CTRL_WRITE 0
66
67#define RTL8366RB_PHY_REG_MASK 0x1f
68#define RTL8366RB_PHY_PAGE_OFFSET 5
69#define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
70#define RTL8366RB_PHY_NO_OFFSET 9
71#define RTL8366RB_PHY_NO_MASK (0x1f << 9)
72
73#define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
74
75/* LED control registers */
76#define RTL8366RB_LED_BLINKRATE_REG 0x0430
77#define RTL8366RB_LED_BLINKRATE_BIT 0
78#define RTL8366RB_LED_BLINKRATE_MASK 0x0007
79
80#define RTL8366RB_LED_CTRL_REG 0x0431
81#define RTL8366RB_LED_0_1_CTRL_REG 0x0432
82#define RTL8366RB_LED_2_3_CTRL_REG 0x0433
83
84#define RTL8366RB_MIB_COUNT 33
85#define RTL8366RB_GLOBAL_MIB_COUNT 1
86#define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
87#define RTL8366RB_MIB_COUNTER_BASE 0x1000
88#define RTL8366RB_MIB_CTRL_REG 0x13F0
89#define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
90#define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
91#define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
92#define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
93#define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
94
95#define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
96#define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
97        (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
98#define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
99#define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
100
101
102#define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
103#define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
104
105
106#define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
107#define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
108#define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
109
110#define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
111
112
113#define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
114#define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
115#define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
116#define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
117#define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
118#define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
119#define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
120
121
122#define RTL8366RB_PORT_NUM_CPU 5
123#define RTL8366RB_NUM_PORTS 6
124#define RTL8366RB_NUM_VLANS 16
125#define RTL8366RB_NUM_LEDGROUPS 4
126#define RTL8366RB_NUM_VIDS 4096
127#define RTL8366RB_PRIORITYMAX 7
128#define RTL8366RB_FIDMAX 7
129
130
131#define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
132#define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
133#define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
134#define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
135#define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
136
137#define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
138
139#define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
140                     RTL8366RB_PORT_2 | \
141                     RTL8366RB_PORT_3 | \
142                     RTL8366RB_PORT_4 | \
143                     RTL8366RB_PORT_5 | \
144                     RTL8366RB_PORT_CPU)
145
146#define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
147                     RTL8366RB_PORT_2 | \
148                     RTL8366RB_PORT_3 | \
149                     RTL8366RB_PORT_4 | \
150                     RTL8366RB_PORT_5)
151
152#define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
153                     RTL8366RB_PORT_2 | \
154                     RTL8366RB_PORT_3 | \
155                     RTL8366RB_PORT_4)
156
157#define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
158
159#define RTL8366RB_VLAN_VID_MASK 0xfff
160#define RTL8366RB_VLAN_PRIORITY_SHIFT 12
161#define RTL8366RB_VLAN_PRIORITY_MASK 0x7
162#define RTL8366RB_VLAN_UNTAG_SHIFT 8
163#define RTL8366RB_VLAN_UNTAG_MASK 0xff
164#define RTL8366RB_VLAN_MEMBER_MASK 0xff
165#define RTL8366RB_VLAN_FID_MASK 0x7
166
167static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
168    { 0, 0, 4, "IfInOctets" },
169    { 0, 4, 4, "EtherStatsOctets" },
170    { 0, 8, 2, "EtherStatsUnderSizePkts" },
171    { 0, 10, 2, "EtherFragments" },
172    { 0, 12, 2, "EtherStatsPkts64Octets" },
173    { 0, 14, 2, "EtherStatsPkts65to127Octets" },
174    { 0, 16, 2, "EtherStatsPkts128to255Octets" },
175    { 0, 18, 2, "EtherStatsPkts256to511Octets" },
176    { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
177    { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
178    { 0, 24, 2, "EtherOversizeStats" },
179    { 0, 26, 2, "EtherStatsJabbers" },
180    { 0, 28, 2, "IfInUcastPkts" },
181    { 0, 30, 2, "EtherStatsMulticastPkts" },
182    { 0, 32, 2, "EtherStatsBroadcastPkts" },
183    { 0, 34, 2, "EtherStatsDropEvents" },
184    { 0, 36, 2, "Dot3StatsFCSErrors" },
185    { 0, 38, 2, "Dot3StatsSymbolErrors" },
186    { 0, 40, 2, "Dot3InPauseFrames" },
187    { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
188    { 0, 44, 4, "IfOutOctets" },
189    { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
190    { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
191    { 0, 52, 2, "Dot3sDeferredTransmissions" },
192    { 0, 54, 2, "Dot3StatsLateCollisions" },
193    { 0, 56, 2, "EtherStatsCollisions" },
194    { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
195    { 0, 60, 2, "Dot3OutPauseFrames" },
196    { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
197    { 0, 64, 2, "Dot1dTpPortInDiscards" },
198    { 0, 66, 2, "IfOutUcastPkts" },
199    { 0, 68, 2, "IfOutMulticastPkts" },
200    { 0, 70, 2, "IfOutBroadcastPkts" },
201};
202
203#define REG_WR(_smi, _reg, _val) \
204    do { \
205        err = rtl8366_smi_write_reg(_smi, _reg, _val); \
206        if (err) \
207            return err; \
208    } while (0)
209
210#define REG_RMW(_smi, _reg, _mask, _val) \
211    do { \
212        err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
213        if (err) \
214            return err; \
215    } while (0)
216
217static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
218{
219    int timeout = 10;
220    u32 data;
221
222    rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
223                  RTL8366RB_CHIP_CTRL_RESET_HW);
224    do {
225        msleep(1);
226        if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
227            return -EIO;
228
229        if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
230            break;
231    } while (--timeout);
232
233    if (!timeout) {
234        printk("Timeout waiting for the switch to reset\n");
235        return -EIO;
236    }
237
238    return 0;
239}
240
241static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
242{
243    int err;
244
245    /* set maximum packet length to 1536 bytes */
246    REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
247        RTL8366RB_SGCR_MAX_LENGTH_1536);
248
249    /* enable all ports */
250    REG_WR(smi, RTL8366RB_PECR, 0);
251
252    /* enable learning for all ports */
253    REG_WR(smi, RTL8366RB_SSCR0, 0);
254
255    /* enable auto ageing for all ports */
256    REG_WR(smi, RTL8366RB_SSCR1, 0);
257
258    /*
259     * discard VLAN tagged packets if the port is not a member of
260     * the VLAN with which the packets is associated.
261     */
262    REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
263
264    /* don't drop packets whose DA has not been learned */
265    REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
266
267    return 0;
268}
269
270static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
271                 u32 phy_no, u32 page, u32 addr, u32 *data)
272{
273    u32 reg;
274    int ret;
275
276    if (phy_no > RTL8366RB_PHY_NO_MAX)
277        return -EINVAL;
278
279    if (page > RTL8366RB_PHY_PAGE_MAX)
280        return -EINVAL;
281
282    if (addr > RTL8366RB_PHY_ADDR_MAX)
283        return -EINVAL;
284
285    ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
286                    RTL8366RB_PHY_CTRL_READ);
287    if (ret)
288        return ret;
289
290    reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
291          ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
292          (addr & RTL8366RB_PHY_REG_MASK);
293
294    ret = rtl8366_smi_write_reg(smi, reg, 0);
295    if (ret)
296        return ret;
297
298    ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
299    if (ret)
300        return ret;
301
302    return 0;
303}
304
305static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
306                  u32 phy_no, u32 page, u32 addr, u32 data)
307{
308    u32 reg;
309    int ret;
310
311    if (phy_no > RTL8366RB_PHY_NO_MAX)
312        return -EINVAL;
313
314    if (page > RTL8366RB_PHY_PAGE_MAX)
315        return -EINVAL;
316
317    if (addr > RTL8366RB_PHY_ADDR_MAX)
318        return -EINVAL;
319
320    ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
321                    RTL8366RB_PHY_CTRL_WRITE);
322    if (ret)
323        return ret;
324
325    reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
326          ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
327          (addr & RTL8366RB_PHY_REG_MASK);
328
329    ret = rtl8366_smi_write_reg(smi, reg, data);
330    if (ret)
331        return ret;
332
333    return 0;
334}
335
336static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
337                     int port, unsigned long long *val)
338{
339    int i;
340    int err;
341    u32 addr, data;
342    u64 mibvalue;
343
344    if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
345        return -EINVAL;
346
347    addr = RTL8366RB_MIB_COUNTER_BASE +
348           RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
349           rtl8366rb_mib_counters[counter].offset;
350
351    /*
352     * Writing access counter address first
353     * then ASIC will prepare 64bits counter wait for being retrived
354     */
355    data = 0; /* writing data will be discard by ASIC */
356    err = rtl8366_smi_write_reg(smi, addr, data);
357    if (err)
358        return err;
359
360    /* read MIB control register */
361    err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
362    if (err)
363        return err;
364
365    if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
366        return -EBUSY;
367
368    if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
369        return -EIO;
370
371    mibvalue = 0;
372    for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
373        err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
374        if (err)
375            return err;
376
377        mibvalue = (mibvalue << 16) | (data & 0xFFFF);
378    }
379
380    *val = mibvalue;
381    return 0;
382}
383
384static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
385                 struct rtl8366_vlan_4k *vlan4k)
386{
387    u32 data[3];
388    int err;
389    int i;
390
391    memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
392
393    if (vid >= RTL8366RB_NUM_VIDS)
394        return -EINVAL;
395
396    /* write VID */
397    err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
398                    vid & RTL8366RB_VLAN_VID_MASK);
399    if (err)
400        return err;
401
402    /* write table access control word */
403    err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
404                    RTL8366RB_TABLE_VLAN_READ_CTRL);
405    if (err)
406        return err;
407
408    for (i = 0; i < 3; i++) {
409        err = rtl8366_smi_read_reg(smi,
410                       RTL8366RB_VLAN_TABLE_READ_BASE + i,
411                       &data[i]);
412        if (err)
413            return err;
414    }
415
416    vlan4k->vid = vid;
417    vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
418            RTL8366RB_VLAN_UNTAG_MASK;
419    vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
420    vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
421
422    return 0;
423}
424
425static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
426                 const struct rtl8366_vlan_4k *vlan4k)
427{
428    u32 data[3];
429    int err;
430    int i;
431
432    if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
433        vlan4k->member > RTL8366RB_PORT_ALL ||
434        vlan4k->untag > RTL8366RB_PORT_ALL ||
435        vlan4k->fid > RTL8366RB_FIDMAX)
436        return -EINVAL;
437
438    data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
439    data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
440          ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
441            RTL8366RB_VLAN_UNTAG_SHIFT);
442    data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
443
444    for (i = 0; i < 3; i++) {
445        err = rtl8366_smi_write_reg(smi,
446                        RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
447                        data[i]);
448        if (err)
449            return err;
450    }
451
452    /* write table access control word */
453    err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
454                    RTL8366RB_TABLE_VLAN_WRITE_CTRL);
455
456    return err;
457}
458
459static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
460                 struct rtl8366_vlan_mc *vlanmc)
461{
462    u32 data[3];
463    int err;
464    int i;
465
466    memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
467
468    if (index >= RTL8366RB_NUM_VLANS)
469        return -EINVAL;
470
471    for (i = 0; i < 3; i++) {
472        err = rtl8366_smi_read_reg(smi,
473                       RTL8366RB_VLAN_MC_BASE(index) + i,
474                       &data[i]);
475        if (err)
476            return err;
477    }
478
479    vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
480    vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
481               RTL8366RB_VLAN_PRIORITY_MASK;
482    vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
483            RTL8366RB_VLAN_UNTAG_MASK;
484    vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
485    vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
486
487    return 0;
488}
489
490static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
491                 const struct rtl8366_vlan_mc *vlanmc)
492{
493    u32 data[3];
494    int err;
495    int i;
496
497    if (index >= RTL8366RB_NUM_VLANS ||
498        vlanmc->vid >= RTL8366RB_NUM_VIDS ||
499        vlanmc->priority > RTL8366RB_PRIORITYMAX ||
500        vlanmc->member > RTL8366RB_PORT_ALL ||
501        vlanmc->untag > RTL8366RB_PORT_ALL ||
502        vlanmc->fid > RTL8366RB_FIDMAX)
503        return -EINVAL;
504
505    data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
506          ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
507            RTL8366RB_VLAN_PRIORITY_SHIFT);
508    data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
509          ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
510            RTL8366RB_VLAN_UNTAG_SHIFT);
511    data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
512
513    for (i = 0; i < 3; i++) {
514        err = rtl8366_smi_write_reg(smi,
515                        RTL8366RB_VLAN_MC_BASE(index) + i,
516                        data[i]);
517        if (err)
518            return err;
519    }
520
521    return 0;
522}
523
524static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
525{
526    u32 data;
527    int err;
528
529    if (port >= RTL8366RB_NUM_PORTS)
530        return -EINVAL;
531
532    err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
533                   &data);
534    if (err)
535        return err;
536
537    *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
538           RTL8366RB_PORT_VLAN_CTRL_MASK;
539
540    return 0;
541
542}
543
544static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
545{
546    if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
547        return -EINVAL;
548
549    return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
550                RTL8366RB_PORT_VLAN_CTRL_MASK <<
551                    RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
552                (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
553                    RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
554}
555
556static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
557{
558    unsigned max = RTL8366RB_NUM_VLANS;
559
560    if (smi->vlan4k_enabled)
561        max = RTL8366RB_NUM_VIDS - 1;
562
563    if (vlan == 0 || vlan >= max)
564        return 0;
565
566    return 1;
567}
568
569static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
570{
571    return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
572                (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
573}
574
575static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
576{
577    return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
578                RTL8366RB_SGCR_EN_VLAN_4KTB,
579                (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
580}
581
582static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
583                  const struct switch_attr *attr,
584                  struct switch_val *val)
585{
586    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
587
588    return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
589                    RTL8366RB_MIB_CTRL_GLOBAL_RESET);
590}
591
592static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
593                     const struct switch_attr *attr,
594                     struct switch_val *val)
595{
596    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
597    u32 data;
598
599    rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
600
601    val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
602
603    return 0;
604}
605
606static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
607                    const struct switch_attr *attr,
608                    struct switch_val *val)
609{
610    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
611
612    if (val->value.i >= 6)
613        return -EINVAL;
614
615    return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
616                RTL8366RB_LED_BLINKRATE_MASK,
617                val->value.i);
618}
619
620static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
621                       const struct switch_attr *attr,
622                       struct switch_val *val)
623{
624    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
625    u32 data;
626
627    rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
628    val->value.i = !data;
629
630    return 0;
631}
632
633
634static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
635                       const struct switch_attr *attr,
636                       struct switch_val *val)
637{
638    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
639    u32 portmask = 0;
640    int err = 0;
641
642    if (!val->value.i)
643        portmask = RTL8366RB_PORT_ALL;
644
645    /* set learning for all ports */
646    REG_WR(smi, RTL8366RB_SSCR0, portmask);
647
648    /* set auto ageing for all ports */
649    REG_WR(smi, RTL8366RB_SSCR1, portmask);
650
651    return 0;
652}
653
654
655static const char *rtl8366rb_speed_str(unsigned speed)
656{
657    switch (speed) {
658    case 0:
659        return "10baseT";
660    case 1:
661        return "100baseT";
662    case 2:
663        return "1000baseT";
664    }
665
666    return "unknown";
667}
668
669static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
670                     const struct switch_attr *attr,
671                     struct switch_val *val)
672{
673    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
674    u32 len = 0, data = 0;
675
676    if (val->port_vlan >= RTL8366RB_NUM_PORTS)
677        return -EINVAL;
678
679    memset(smi->buf, '\0', sizeof(smi->buf));
680    rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
681                 (val->port_vlan / 2), &data);
682
683    if (val->port_vlan % 2)
684        data = data >> 8;
685
686    if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
687        len = snprintf(smi->buf, sizeof(smi->buf),
688                "port:%d link:up speed:%s %s-duplex %s%s%s",
689                val->port_vlan,
690                rtl8366rb_speed_str(data &
691                      RTL8366RB_PORT_STATUS_SPEED_MASK),
692                (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
693                    "full" : "half",
694                (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
695                    "tx-pause ": "",
696                (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
697                    "rx-pause " : "",
698                (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
699                    "nway ": "");
700    } else {
701        len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
702                val->port_vlan);
703    }
704
705    val->value.s = smi->buf;
706    val->len = len;
707
708    return 0;
709}
710
711static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
712                    const struct switch_attr *attr,
713                    struct switch_val *val)
714{
715    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
716    u32 data;
717    u32 mask;
718    u32 reg;
719
720    if (val->port_vlan >= RTL8366RB_NUM_PORTS)
721        return -EINVAL;
722
723    if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
724        reg = RTL8366RB_LED_BLINKRATE_REG;
725        mask = 0xF << 4;
726        data = val->value.i << 4;
727    } else {
728        reg = RTL8366RB_LED_CTRL_REG;
729        mask = 0xF << (val->port_vlan * 4),
730        data = val->value.i << (val->port_vlan * 4);
731    }
732
733    return rtl8366_smi_rmwr(smi, reg, mask, data);
734}
735
736static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
737                    const struct switch_attr *attr,
738                    struct switch_val *val)
739{
740    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
741    u32 data = 0;
742
743    if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
744        return -EINVAL;
745
746    rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
747    val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
748
749    return 0;
750}
751
752static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
753                       const struct switch_attr *attr,
754                       struct switch_val *val)
755{
756    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
757
758    if (val->port_vlan >= RTL8366RB_NUM_PORTS)
759        return -EINVAL;
760
761    return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
762                RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
763}
764
765static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
766{
767    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
768    int err;
769
770    err = rtl8366rb_reset_chip(smi);
771    if (err)
772        return err;
773
774    err = rtl8366rb_hw_init(smi);
775    if (err)
776        return err;
777
778    return rtl8366_reset_vlan(smi);
779}
780
781static struct switch_attr rtl8366rb_globals[] = {
782    {
783        .type = SWITCH_TYPE_INT,
784        .name = "enable_learning",
785        .description = "Enable learning, enable aging",
786        .set = rtl8366rb_sw_set_learning_enable,
787        .get = rtl8366rb_sw_get_learning_enable,
788        .max = 1
789    }, {
790        .type = SWITCH_TYPE_INT,
791        .name = "enable_vlan",
792        .description = "Enable VLAN mode",
793        .set = rtl8366_sw_set_vlan_enable,
794        .get = rtl8366_sw_get_vlan_enable,
795        .max = 1,
796        .ofs = 1
797    }, {
798        .type = SWITCH_TYPE_INT,
799        .name = "enable_vlan4k",
800        .description = "Enable VLAN 4K mode",
801        .set = rtl8366_sw_set_vlan_enable,
802        .get = rtl8366_sw_get_vlan_enable,
803        .max = 1,
804        .ofs = 2
805    }, {
806        .type = SWITCH_TYPE_NOVAL,
807        .name = "reset_mibs",
808        .description = "Reset all MIB counters",
809        .set = rtl8366rb_sw_reset_mibs,
810    }, {
811        .type = SWITCH_TYPE_INT,
812        .name = "blinkrate",
813        .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
814        " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
815        .set = rtl8366rb_sw_set_blinkrate,
816        .get = rtl8366rb_sw_get_blinkrate,
817        .max = 5
818    },
819};
820
821static struct switch_attr rtl8366rb_port[] = {
822    {
823        .type = SWITCH_TYPE_STRING,
824        .name = "link",
825        .description = "Get port link information",
826        .max = 1,
827        .set = NULL,
828        .get = rtl8366rb_sw_get_port_link,
829    }, {
830        .type = SWITCH_TYPE_NOVAL,
831        .name = "reset_mib",
832        .description = "Reset single port MIB counters",
833        .set = rtl8366rb_sw_reset_port_mibs,
834    }, {
835        .type = SWITCH_TYPE_STRING,
836        .name = "mib",
837        .description = "Get MIB counters for port",
838        .max = 33,
839        .set = NULL,
840        .get = rtl8366_sw_get_port_mib,
841    }, {
842        .type = SWITCH_TYPE_INT,
843        .name = "led",
844        .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
845        .max = 15,
846        .set = rtl8366rb_sw_set_port_led,
847        .get = rtl8366rb_sw_get_port_led,
848    },
849};
850
851static struct switch_attr rtl8366rb_vlan[] = {
852    {
853        .type = SWITCH_TYPE_STRING,
854        .name = "info",
855        .description = "Get vlan information",
856        .max = 1,
857        .set = NULL,
858        .get = rtl8366_sw_get_vlan_info,
859    },
860};
861
862static const struct switch_dev_ops rtl8366_ops = {
863    .attr_global = {
864        .attr = rtl8366rb_globals,
865        .n_attr = ARRAY_SIZE(rtl8366rb_globals),
866    },
867    .attr_port = {
868        .attr = rtl8366rb_port,
869        .n_attr = ARRAY_SIZE(rtl8366rb_port),
870    },
871    .attr_vlan = {
872        .attr = rtl8366rb_vlan,
873        .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
874    },
875
876    .get_vlan_ports = rtl8366_sw_get_vlan_ports,
877    .set_vlan_ports = rtl8366_sw_set_vlan_ports,
878    .get_port_pvid = rtl8366_sw_get_port_pvid,
879    .set_port_pvid = rtl8366_sw_set_port_pvid,
880    .reset_switch = rtl8366rb_sw_reset_switch,
881};
882
883static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
884{
885    struct switch_dev *dev = &smi->sw_dev;
886    int err;
887
888    dev->name = "RTL8366RB";
889    dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
890    dev->ports = RTL8366RB_NUM_PORTS;
891    dev->vlans = RTL8366RB_NUM_VIDS;
892    dev->ops = &rtl8366_ops;
893    dev->devname = dev_name(smi->parent);
894
895    err = register_switch(dev, NULL);
896    if (err)
897        dev_err(smi->parent, "switch registration failed\n");
898
899    return err;
900}
901
902static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
903{
904    unregister_switch(&smi->sw_dev);
905}
906
907static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
908{
909    struct rtl8366_smi *smi = bus->priv;
910    u32 val = 0;
911    int err;
912
913    err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
914    if (err)
915        return 0xffff;
916
917    return val;
918}
919
920static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
921{
922    struct rtl8366_smi *smi = bus->priv;
923    u32 t;
924    int err;
925
926    err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
927    /* flush write */
928    (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
929
930    return err;
931}
932
933static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
934{
935    return (bus->read == rtl8366rb_mii_read &&
936        bus->write == rtl8366rb_mii_write);
937}
938
939static int rtl8366rb_setup(struct rtl8366_smi *smi)
940{
941    int ret;
942
943    ret = rtl8366rb_reset_chip(smi);
944    if (ret)
945        return ret;
946
947    ret = rtl8366rb_hw_init(smi);
948    return ret;
949}
950
951static int rtl8366rb_detect(struct rtl8366_smi *smi)
952{
953    u32 chip_id = 0;
954    u32 chip_ver = 0;
955    int ret;
956
957    ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
958    if (ret) {
959        dev_err(smi->parent, "unable to read chip id\n");
960        return ret;
961    }
962
963    switch (chip_id) {
964    case RTL8366RB_CHIP_ID_8366:
965        break;
966    default:
967        dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
968        return -ENODEV;
969    }
970
971    ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
972                   &chip_ver);
973    if (ret) {
974        dev_err(smi->parent, "unable to read chip version\n");
975        return ret;
976    }
977
978    dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
979         chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
980
981    return 0;
982}
983
984static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
985    .detect = rtl8366rb_detect,
986    .setup = rtl8366rb_setup,
987
988    .mii_read = rtl8366rb_mii_read,
989    .mii_write = rtl8366rb_mii_write,
990
991    .get_vlan_mc = rtl8366rb_get_vlan_mc,
992    .set_vlan_mc = rtl8366rb_set_vlan_mc,
993    .get_vlan_4k = rtl8366rb_get_vlan_4k,
994    .set_vlan_4k = rtl8366rb_set_vlan_4k,
995    .get_mc_index = rtl8366rb_get_mc_index,
996    .set_mc_index = rtl8366rb_set_mc_index,
997    .get_mib_counter = rtl8366rb_get_mib_counter,
998    .is_vlan_valid = rtl8366rb_is_vlan_valid,
999    .enable_vlan = rtl8366rb_enable_vlan,
1000    .enable_vlan4k = rtl8366rb_enable_vlan4k,
1001};
1002
1003static int __init rtl8366rb_probe(struct platform_device *pdev)
1004{
1005    static int rtl8366_smi_version_printed;
1006    struct rtl8366rb_platform_data *pdata;
1007    struct rtl8366_smi *smi;
1008    int err;
1009
1010    if (!rtl8366_smi_version_printed++)
1011        printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1012               " version " RTL8366RB_DRIVER_VER"\n");
1013
1014    pdata = pdev->dev.platform_data;
1015    if (!pdata) {
1016        dev_err(&pdev->dev, "no platform data specified\n");
1017        err = -EINVAL;
1018        goto err_out;
1019    }
1020
1021    smi = rtl8366_smi_alloc(&pdev->dev);
1022    if (!smi) {
1023        err = -ENOMEM;
1024        goto err_out;
1025    }
1026
1027    smi->gpio_sda = pdata->gpio_sda;
1028    smi->gpio_sck = pdata->gpio_sck;
1029    smi->ops = &rtl8366rb_smi_ops;
1030    smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1031    smi->num_ports = RTL8366RB_NUM_PORTS;
1032    smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1033    smi->mib_counters = rtl8366rb_mib_counters;
1034    smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1035
1036    err = rtl8366_smi_init(smi);
1037    if (err)
1038        goto err_free_smi;
1039
1040    platform_set_drvdata(pdev, smi);
1041
1042    err = rtl8366rb_switch_init(smi);
1043    if (err)
1044        goto err_clear_drvdata;
1045
1046    return 0;
1047
1048 err_clear_drvdata:
1049    platform_set_drvdata(pdev, NULL);
1050    rtl8366_smi_cleanup(smi);
1051 err_free_smi:
1052    kfree(smi);
1053 err_out:
1054    return err;
1055}
1056
1057static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1058{
1059    if (!rtl8366rb_mii_bus_match(phydev->bus))
1060        return -EINVAL;
1061
1062    return 0;
1063}
1064
1065static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1066{
1067    /* phy 4 might be connected to a second mac, allow aneg config */
1068    if (phydev->addr == RTL8366RB_PHY_WAN)
1069        return genphy_config_aneg(phydev);
1070
1071    return 0;
1072}
1073
1074static struct phy_driver rtl8366rb_phy_driver = {
1075    .phy_id = 0x001cc960,
1076    .name = "Realtek RTL8366RB",
1077    .phy_id_mask = 0x1ffffff0,
1078    .features = PHY_GBIT_FEATURES,
1079    .config_aneg = rtl8366rb_phy_config_aneg,
1080    .config_init = rtl8366rb_phy_config_init,
1081    .read_status = genphy_read_status,
1082    .driver = {
1083        .owner = THIS_MODULE,
1084    },
1085};
1086
1087static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1088{
1089    struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1090
1091    if (smi) {
1092        rtl8366rb_switch_cleanup(smi);
1093        platform_set_drvdata(pdev, NULL);
1094        rtl8366_smi_cleanup(smi);
1095        kfree(smi);
1096    }
1097
1098    return 0;
1099}
1100
1101static struct platform_driver rtl8366rb_driver = {
1102    .driver = {
1103        .name = RTL8366RB_DRIVER_NAME,
1104        .owner = THIS_MODULE,
1105    },
1106    .probe = rtl8366rb_probe,
1107    .remove = __devexit_p(rtl8366rb_remove),
1108};
1109
1110static int __init rtl8366rb_module_init(void)
1111{
1112    int ret;
1113    ret = platform_driver_register(&rtl8366rb_driver);
1114    if (ret)
1115        return ret;
1116
1117    ret = phy_driver_register(&rtl8366rb_phy_driver);
1118    if (ret)
1119        goto err_platform_unregister;
1120
1121    return 0;
1122
1123 err_platform_unregister:
1124    platform_driver_unregister(&rtl8366rb_driver);
1125    return ret;
1126}
1127module_init(rtl8366rb_module_init);
1128
1129static void __exit rtl8366rb_module_exit(void)
1130{
1131    phy_driver_unregister(&rtl8366rb_phy_driver);
1132    platform_driver_unregister(&rtl8366rb_driver);
1133}
1134module_exit(rtl8366rb_module_exit);
1135
1136MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1137MODULE_VERSION(RTL8366RB_DRIVER_VER);
1138MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1139MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1140MODULE_LICENSE("GPL v2");
1141MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
1142

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