Root/target/linux/generic-2.6/files/drivers/net/phy/rtl8366s.c

1/*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/skbuff.h>
18#include <linux/rtl8366s.h>
19
20#include "rtl8366_smi.h"
21
22#define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
23#define RTL8366S_DRIVER_VER "0.2.2"
24
25#define RTL8366S_PHY_NO_MAX 4
26#define RTL8366S_PHY_PAGE_MAX 7
27#define RTL8366S_PHY_ADDR_MAX 31
28#define RTL8366S_PHY_WAN 4
29
30/* Switch Global Configuration register */
31#define RTL8366S_SGCR 0x0000
32#define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
33#define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
34#define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
35#define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
36#define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
37#define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
38#define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
39#define RTL8366S_SGCR_EN_VLAN BIT(13)
40
41/* Port Enable Control register */
42#define RTL8366S_PECR 0x0001
43
44/* Switch Security Control registers */
45#define RTL8366S_SSCR0 0x0002
46#define RTL8366S_SSCR1 0x0003
47#define RTL8366S_SSCR2 0x0004
48#define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
49
50#define RTL8366S_RESET_CTRL_REG 0x0100
51#define RTL8366S_CHIP_CTRL_RESET_HW 1
52#define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
53
54#define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
55#define RTL8366S_CHIP_VERSION_MASK 0xf
56#define RTL8366S_CHIP_ID_REG 0x0105
57#define RTL8366S_CHIP_ID_8366 0x8366
58
59/* PHY registers control */
60#define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
61#define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
62
63#define RTL8366S_PHY_CTRL_READ 1
64#define RTL8366S_PHY_CTRL_WRITE 0
65
66#define RTL8366S_PHY_REG_MASK 0x1f
67#define RTL8366S_PHY_PAGE_OFFSET 5
68#define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
69#define RTL8366S_PHY_NO_OFFSET 9
70#define RTL8366S_PHY_NO_MASK (0x1f << 9)
71
72/* LED control registers */
73#define RTL8366S_LED_BLINKRATE_REG 0x0420
74#define RTL8366S_LED_BLINKRATE_BIT 0
75#define RTL8366S_LED_BLINKRATE_MASK 0x0007
76
77#define RTL8366S_LED_CTRL_REG 0x0421
78#define RTL8366S_LED_0_1_CTRL_REG 0x0422
79#define RTL8366S_LED_2_3_CTRL_REG 0x0423
80
81#define RTL8366S_MIB_COUNT 33
82#define RTL8366S_GLOBAL_MIB_COUNT 1
83#define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
84#define RTL8366S_MIB_COUNTER_BASE 0x1000
85#define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
86#define RTL8366S_MIB_COUNTER_BASE2 0x1180
87#define RTL8366S_MIB_CTRL_REG 0x11F0
88#define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
89#define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
90#define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
91
92#define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
93#define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
94#define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
95
96
97#define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
98#define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
99        (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
100#define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
101#define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
102
103
104#define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
105#define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
106
107#define RTL8366S_VLAN_TB_CTRL_REG 0x010F
108
109#define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
110#define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
111#define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
112
113#define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2)
114
115#define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379
116
117#define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
118#define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
119#define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
120#define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
121#define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
122#define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
123#define RTL8366S_PORT_STATUS_AN_MASK 0x0080
124
125
126#define RTL8366S_PORT_NUM_CPU 5
127#define RTL8366S_NUM_PORTS 6
128#define RTL8366S_NUM_VLANS 16
129#define RTL8366S_NUM_LEDGROUPS 4
130#define RTL8366S_NUM_VIDS 4096
131#define RTL8366S_PRIORITYMAX 7
132#define RTL8366S_FIDMAX 7
133
134
135#define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
136#define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
137#define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
138#define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
139
140#define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
141#define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
142
143#define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
144                     RTL8366S_PORT_2 | \
145                     RTL8366S_PORT_3 | \
146                     RTL8366S_PORT_4 | \
147                     RTL8366S_PORT_UNKNOWN | \
148                     RTL8366S_PORT_CPU)
149
150#define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
151                     RTL8366S_PORT_2 | \
152                     RTL8366S_PORT_3 | \
153                     RTL8366S_PORT_4 | \
154                     RTL8366S_PORT_UNKNOWN)
155
156#define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
157                     RTL8366S_PORT_2 | \
158                     RTL8366S_PORT_3 | \
159                     RTL8366S_PORT_4)
160
161#define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
162                     RTL8366S_PORT_CPU)
163
164#define RTL8366S_VLAN_VID_MASK 0xfff
165#define RTL8366S_VLAN_PRIORITY_SHIFT 12
166#define RTL8366S_VLAN_PRIORITY_MASK 0x7
167#define RTL8366S_VLAN_MEMBER_MASK 0x3f
168#define RTL8366S_VLAN_UNTAG_SHIFT 6
169#define RTL8366S_VLAN_UNTAG_MASK 0x3f
170#define RTL8366S_VLAN_FID_SHIFT 12
171#define RTL8366S_VLAN_FID_MASK 0x7
172
173static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
174    { 0, 0, 4, "IfInOctets" },
175    { 0, 4, 4, "EtherStatsOctets" },
176    { 0, 8, 2, "EtherStatsUnderSizePkts" },
177    { 0, 10, 2, "EtherFragments" },
178    { 0, 12, 2, "EtherStatsPkts64Octets" },
179    { 0, 14, 2, "EtherStatsPkts65to127Octets" },
180    { 0, 16, 2, "EtherStatsPkts128to255Octets" },
181    { 0, 18, 2, "EtherStatsPkts256to511Octets" },
182    { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
183    { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
184    { 0, 24, 2, "EtherOversizeStats" },
185    { 0, 26, 2, "EtherStatsJabbers" },
186    { 0, 28, 2, "IfInUcastPkts" },
187    { 0, 30, 2, "EtherStatsMulticastPkts" },
188    { 0, 32, 2, "EtherStatsBroadcastPkts" },
189    { 0, 34, 2, "EtherStatsDropEvents" },
190    { 0, 36, 2, "Dot3StatsFCSErrors" },
191    { 0, 38, 2, "Dot3StatsSymbolErrors" },
192    { 0, 40, 2, "Dot3InPauseFrames" },
193    { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
194    { 0, 44, 4, "IfOutOctets" },
195    { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
196    { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
197    { 0, 52, 2, "Dot3sDeferredTransmissions" },
198    { 0, 54, 2, "Dot3StatsLateCollisions" },
199    { 0, 56, 2, "EtherStatsCollisions" },
200    { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
201    { 0, 60, 2, "Dot3OutPauseFrames" },
202    { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
203
204    /*
205     * The following counters are accessible at a different
206     * base address.
207     */
208    { 1, 0, 2, "Dot1dTpPortInDiscards" },
209    { 1, 2, 2, "IfOutUcastPkts" },
210    { 1, 4, 2, "IfOutMulticastPkts" },
211    { 1, 6, 2, "IfOutBroadcastPkts" },
212};
213
214#define REG_WR(_smi, _reg, _val) \
215    do { \
216        err = rtl8366_smi_write_reg(_smi, _reg, _val); \
217        if (err) \
218            return err; \
219    } while (0)
220
221#define REG_RMW(_smi, _reg, _mask, _val) \
222    do { \
223        err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
224        if (err) \
225            return err; \
226    } while (0)
227
228static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
229{
230    int timeout = 10;
231    u32 data;
232
233    rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
234                  RTL8366S_CHIP_CTRL_RESET_HW);
235    do {
236        msleep(1);
237        if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
238            return -EIO;
239
240        if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
241            break;
242    } while (--timeout);
243
244    if (!timeout) {
245        printk("Timeout waiting for the switch to reset\n");
246        return -EIO;
247    }
248
249    return 0;
250}
251
252static int rtl8366s_hw_init(struct rtl8366_smi *smi)
253{
254    int err;
255
256    /* set maximum packet length to 1536 bytes */
257    REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
258        RTL8366S_SGCR_MAX_LENGTH_1536);
259
260    /* enable all ports */
261    REG_WR(smi, RTL8366S_PECR, 0);
262
263    /* enable learning for all ports */
264    REG_WR(smi, RTL8366S_SSCR0, 0);
265
266    /* enable auto ageing for all ports */
267    REG_WR(smi, RTL8366S_SSCR1, 0);
268
269    /*
270     * discard VLAN tagged packets if the port is not a member of
271     * the VLAN with which the packets is associated.
272     */
273    REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
274
275    /* don't drop packets whose DA has not been learned */
276    REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
277
278    return 0;
279}
280
281static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
282                 u32 phy_no, u32 page, u32 addr, u32 *data)
283{
284    u32 reg;
285    int ret;
286
287    if (phy_no > RTL8366S_PHY_NO_MAX)
288        return -EINVAL;
289
290    if (page > RTL8366S_PHY_PAGE_MAX)
291        return -EINVAL;
292
293    if (addr > RTL8366S_PHY_ADDR_MAX)
294        return -EINVAL;
295
296    ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
297                    RTL8366S_PHY_CTRL_READ);
298    if (ret)
299        return ret;
300
301    reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
302          ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
303          (addr & RTL8366S_PHY_REG_MASK);
304
305    ret = rtl8366_smi_write_reg(smi, reg, 0);
306    if (ret)
307        return ret;
308
309    ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
310    if (ret)
311        return ret;
312
313    return 0;
314}
315
316static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
317                  u32 phy_no, u32 page, u32 addr, u32 data)
318{
319    u32 reg;
320    int ret;
321
322    if (phy_no > RTL8366S_PHY_NO_MAX)
323        return -EINVAL;
324
325    if (page > RTL8366S_PHY_PAGE_MAX)
326        return -EINVAL;
327
328    if (addr > RTL8366S_PHY_ADDR_MAX)
329        return -EINVAL;
330
331    ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
332                    RTL8366S_PHY_CTRL_WRITE);
333    if (ret)
334        return ret;
335
336    reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
337          ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
338          (addr & RTL8366S_PHY_REG_MASK);
339
340    ret = rtl8366_smi_write_reg(smi, reg, data);
341    if (ret)
342        return ret;
343
344    return 0;
345}
346
347static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
348                   int port, unsigned long long *val)
349{
350    int i;
351    int err;
352    u32 addr, data;
353    u64 mibvalue;
354
355    if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
356        return -EINVAL;
357
358    switch (rtl8366s_mib_counters[counter].base) {
359    case 0:
360        addr = RTL8366S_MIB_COUNTER_BASE +
361               RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
362        break;
363
364    case 1:
365        addr = RTL8366S_MIB_COUNTER_BASE2 +
366            RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
367        break;
368
369    default:
370        return -EINVAL;
371    }
372
373    addr += rtl8366s_mib_counters[counter].offset;
374
375    /*
376     * Writing access counter address first
377     * then ASIC will prepare 64bits counter wait for being retrived
378     */
379    data = 0; /* writing data will be discard by ASIC */
380    err = rtl8366_smi_write_reg(smi, addr, data);
381    if (err)
382        return err;
383
384    /* read MIB control register */
385    err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
386    if (err)
387        return err;
388
389    if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
390        return -EBUSY;
391
392    if (data & RTL8366S_MIB_CTRL_RESET_MASK)
393        return -EIO;
394
395    mibvalue = 0;
396    for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
397        err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
398        if (err)
399            return err;
400
401        mibvalue = (mibvalue << 16) | (data & 0xFFFF);
402    }
403
404    *val = mibvalue;
405    return 0;
406}
407
408static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
409                struct rtl8366_vlan_4k *vlan4k)
410{
411    u32 data[2];
412    int err;
413    int i;
414
415    memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
416
417    if (vid >= RTL8366S_NUM_VIDS)
418        return -EINVAL;
419
420    /* write VID */
421    err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
422                    vid & RTL8366S_VLAN_VID_MASK);
423    if (err)
424        return err;
425
426    /* write table access control word */
427    err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
428                    RTL8366S_TABLE_VLAN_READ_CTRL);
429    if (err)
430        return err;
431
432    for (i = 0; i < 2; i++) {
433        err = rtl8366_smi_read_reg(smi,
434                       RTL8366S_VLAN_TABLE_READ_BASE + i,
435                       &data[i]);
436        if (err)
437            return err;
438    }
439
440    vlan4k->vid = vid;
441    vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
442            RTL8366S_VLAN_UNTAG_MASK;
443    vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
444    vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
445            RTL8366S_VLAN_FID_MASK;
446
447    return 0;
448}
449
450static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
451                const struct rtl8366_vlan_4k *vlan4k)
452{
453    u32 data[2];
454    int err;
455    int i;
456
457    if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
458        vlan4k->member > RTL8366S_PORT_ALL ||
459        vlan4k->untag > RTL8366S_PORT_ALL ||
460        vlan4k->fid > RTL8366S_FIDMAX)
461        return -EINVAL;
462
463    data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
464    data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
465          ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
466            RTL8366S_VLAN_UNTAG_SHIFT) |
467          ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
468            RTL8366S_VLAN_FID_SHIFT);
469
470    for (i = 0; i < 2; i++) {
471        err = rtl8366_smi_write_reg(smi,
472                        RTL8366S_VLAN_TABLE_WRITE_BASE + i,
473                        data[i]);
474        if (err)
475            return err;
476    }
477
478    /* write table access control word */
479    err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
480                    RTL8366S_TABLE_VLAN_WRITE_CTRL);
481
482    return err;
483}
484
485static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
486                struct rtl8366_vlan_mc *vlanmc)
487{
488    u32 data[2];
489    int err;
490    int i;
491
492    memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
493
494    if (index >= RTL8366S_NUM_VLANS)
495        return -EINVAL;
496
497    for (i = 0; i < 2; i++) {
498        err = rtl8366_smi_read_reg(smi,
499                       RTL8366S_VLAN_MC_BASE(index) + i,
500                       &data[i]);
501        if (err)
502            return err;
503    }
504
505    vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
506    vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
507               RTL8366S_VLAN_PRIORITY_MASK;
508    vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
509            RTL8366S_VLAN_UNTAG_MASK;
510    vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
511    vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
512              RTL8366S_VLAN_FID_MASK;
513
514    return 0;
515}
516
517static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
518                const struct rtl8366_vlan_mc *vlanmc)
519{
520    u32 data[2];
521    int err;
522    int i;
523
524    if (index >= RTL8366S_NUM_VLANS ||
525        vlanmc->vid >= RTL8366S_NUM_VIDS ||
526        vlanmc->priority > RTL8366S_PRIORITYMAX ||
527        vlanmc->member > RTL8366S_PORT_ALL ||
528        vlanmc->untag > RTL8366S_PORT_ALL ||
529        vlanmc->fid > RTL8366S_FIDMAX)
530        return -EINVAL;
531
532    data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
533          ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
534            RTL8366S_VLAN_PRIORITY_SHIFT);
535    data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
536          ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
537            RTL8366S_VLAN_UNTAG_SHIFT) |
538          ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
539            RTL8366S_VLAN_FID_SHIFT);
540
541    for (i = 0; i < 2; i++) {
542        err = rtl8366_smi_write_reg(smi,
543                        RTL8366S_VLAN_MC_BASE(index) + i,
544                        data[i]);
545        if (err)
546            return err;
547    }
548
549    return 0;
550}
551
552static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
553{
554    u32 data;
555    int err;
556
557    if (port >= RTL8366S_NUM_PORTS)
558        return -EINVAL;
559
560    err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
561                   &data);
562    if (err)
563        return err;
564
565    *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
566           RTL8366S_PORT_VLAN_CTRL_MASK;
567
568    return 0;
569}
570
571static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
572{
573    if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
574        return -EINVAL;
575
576    return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
577                RTL8366S_PORT_VLAN_CTRL_MASK <<
578                    RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
579                (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
580                    RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
581}
582
583static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable)
584{
585    return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
586                (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
587}
588
589static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable)
590{
591    return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
592                1, (enable) ? 1 : 0);
593}
594
595static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
596{
597    unsigned max = RTL8366S_NUM_VLANS;
598
599    if (smi->vlan4k_enabled)
600        max = RTL8366S_NUM_VIDS - 1;
601
602    if (vlan == 0 || vlan >= max)
603        return 0;
604
605    return 1;
606}
607
608static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
609                  const struct switch_attr *attr,
610                  struct switch_val *val)
611{
612    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
613
614    return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
615}
616
617static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
618                     const struct switch_attr *attr,
619                     struct switch_val *val)
620{
621    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
622    u32 data;
623
624    rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
625
626    val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
627
628    return 0;
629}
630
631static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
632                    const struct switch_attr *attr,
633                    struct switch_val *val)
634{
635    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
636
637    if (val->value.i >= 6)
638        return -EINVAL;
639
640    return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
641                RTL8366S_LED_BLINKRATE_MASK,
642                val->value.i);
643}
644
645static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
646                       const struct switch_attr *attr,
647                       struct switch_val *val)
648{
649    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
650    u32 data;
651
652    rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
653    val->value.i = !data;
654
655    return 0;
656}
657
658
659static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
660                       const struct switch_attr *attr,
661                       struct switch_val *val)
662{
663    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
664    u32 portmask = 0;
665    int err = 0;
666
667    if (!val->value.i)
668        portmask = RTL8366S_PORT_ALL;
669
670    /* set learning for all ports */
671    REG_WR(smi, RTL8366S_SSCR0, portmask);
672
673    /* set auto ageing for all ports */
674    REG_WR(smi, RTL8366S_SSCR1, portmask);
675
676    return 0;
677}
678
679
680static const char *rtl8366s_speed_str(unsigned speed)
681{
682    switch (speed) {
683    case 0:
684        return "10baseT";
685    case 1:
686        return "100baseT";
687    case 2:
688        return "1000baseT";
689    }
690
691    return "unknown";
692}
693
694static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
695                     const struct switch_attr *attr,
696                     struct switch_val *val)
697{
698    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
699    u32 len = 0, data = 0;
700
701    if (val->port_vlan >= RTL8366S_NUM_PORTS)
702        return -EINVAL;
703
704    memset(smi->buf, '\0', sizeof(smi->buf));
705    rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
706                 (val->port_vlan / 2), &data);
707
708    if (val->port_vlan % 2)
709        data = data >> 8;
710
711    if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
712        len = snprintf(smi->buf, sizeof(smi->buf),
713                "port:%d link:up speed:%s %s-duplex %s%s%s",
714                val->port_vlan,
715                rtl8366s_speed_str(data &
716                      RTL8366S_PORT_STATUS_SPEED_MASK),
717                (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
718                    "full" : "half",
719                (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
720                    "tx-pause ": "",
721                (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
722                    "rx-pause " : "",
723                (data & RTL8366S_PORT_STATUS_AN_MASK) ?
724                    "nway ": "");
725    } else {
726        len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
727                val->port_vlan);
728    }
729
730    val->value.s = smi->buf;
731    val->len = len;
732
733    return 0;
734}
735
736static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
737                    const struct switch_attr *attr,
738                    struct switch_val *val)
739{
740    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
741    u32 data;
742    u32 mask;
743    u32 reg;
744
745    if (val->port_vlan >= RTL8366S_NUM_PORTS ||
746        (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
747        return -EINVAL;
748
749    if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
750        reg = RTL8366S_LED_BLINKRATE_REG;
751        mask = 0xF << 4;
752        data = val->value.i << 4;
753    } else {
754        reg = RTL8366S_LED_CTRL_REG;
755        mask = 0xF << (val->port_vlan * 4),
756        data = val->value.i << (val->port_vlan * 4);
757    }
758
759    return rtl8366_smi_rmwr(smi, reg, mask, data);
760}
761
762static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
763                    const struct switch_attr *attr,
764                    struct switch_val *val)
765{
766    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
767    u32 data = 0;
768
769    if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
770        return -EINVAL;
771
772    rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
773    val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
774
775    return 0;
776}
777
778static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
779                       const struct switch_attr *attr,
780                       struct switch_val *val)
781{
782    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
783
784    if (val->port_vlan >= RTL8366S_NUM_PORTS)
785        return -EINVAL;
786
787
788    return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
789                0, (1 << (val->port_vlan + 3)));
790}
791
792static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
793{
794    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
795    int err;
796
797    err = rtl8366s_reset_chip(smi);
798    if (err)
799        return err;
800
801    err = rtl8366s_hw_init(smi);
802    if (err)
803        return err;
804
805    return rtl8366_reset_vlan(smi);
806}
807
808static struct switch_attr rtl8366s_globals[] = {
809    {
810        .type = SWITCH_TYPE_INT,
811        .name = "enable_learning",
812        .description = "Enable learning, enable aging",
813        .set = rtl8366s_sw_set_learning_enable,
814        .get = rtl8366s_sw_get_learning_enable,
815        .max = 1,
816    }, {
817        .type = SWITCH_TYPE_INT,
818        .name = "enable_vlan",
819        .description = "Enable VLAN mode",
820        .set = rtl8366_sw_set_vlan_enable,
821        .get = rtl8366_sw_get_vlan_enable,
822        .max = 1,
823        .ofs = 1
824    }, {
825        .type = SWITCH_TYPE_INT,
826        .name = "enable_vlan4k",
827        .description = "Enable VLAN 4K mode",
828        .set = rtl8366_sw_set_vlan_enable,
829        .get = rtl8366_sw_get_vlan_enable,
830        .max = 1,
831        .ofs = 2
832    }, {
833        .type = SWITCH_TYPE_NOVAL,
834        .name = "reset_mibs",
835        .description = "Reset all MIB counters",
836        .set = rtl8366s_sw_reset_mibs,
837    }, {
838        .type = SWITCH_TYPE_INT,
839        .name = "blinkrate",
840        .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
841        " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
842        .set = rtl8366s_sw_set_blinkrate,
843        .get = rtl8366s_sw_get_blinkrate,
844        .max = 5
845    },
846};
847
848static struct switch_attr rtl8366s_port[] = {
849    {
850        .type = SWITCH_TYPE_STRING,
851        .name = "link",
852        .description = "Get port link information",
853        .max = 1,
854        .set = NULL,
855        .get = rtl8366s_sw_get_port_link,
856    }, {
857        .type = SWITCH_TYPE_NOVAL,
858        .name = "reset_mib",
859        .description = "Reset single port MIB counters",
860        .set = rtl8366s_sw_reset_port_mibs,
861    }, {
862        .type = SWITCH_TYPE_STRING,
863        .name = "mib",
864        .description = "Get MIB counters for port",
865        .max = 33,
866        .set = NULL,
867        .get = rtl8366_sw_get_port_mib,
868    }, {
869        .type = SWITCH_TYPE_INT,
870        .name = "led",
871        .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
872        .max = 15,
873        .set = rtl8366s_sw_set_port_led,
874        .get = rtl8366s_sw_get_port_led,
875    },
876};
877
878static struct switch_attr rtl8366s_vlan[] = {
879    {
880        .type = SWITCH_TYPE_STRING,
881        .name = "info",
882        .description = "Get vlan information",
883        .max = 1,
884        .set = NULL,
885        .get = rtl8366_sw_get_vlan_info,
886    },
887};
888
889static const struct switch_dev_ops rtl8366_ops = {
890    .attr_global = {
891        .attr = rtl8366s_globals,
892        .n_attr = ARRAY_SIZE(rtl8366s_globals),
893    },
894    .attr_port = {
895        .attr = rtl8366s_port,
896        .n_attr = ARRAY_SIZE(rtl8366s_port),
897    },
898    .attr_vlan = {
899        .attr = rtl8366s_vlan,
900        .n_attr = ARRAY_SIZE(rtl8366s_vlan),
901    },
902
903    .get_vlan_ports = rtl8366_sw_get_vlan_ports,
904    .set_vlan_ports = rtl8366_sw_set_vlan_ports,
905    .get_port_pvid = rtl8366_sw_get_port_pvid,
906    .set_port_pvid = rtl8366_sw_set_port_pvid,
907    .reset_switch = rtl8366s_sw_reset_switch,
908};
909
910static int rtl8366s_switch_init(struct rtl8366_smi *smi)
911{
912    struct switch_dev *dev = &smi->sw_dev;
913    int err;
914
915    dev->name = "RTL8366S";
916    dev->cpu_port = RTL8366S_PORT_NUM_CPU;
917    dev->ports = RTL8366S_NUM_PORTS;
918    dev->vlans = RTL8366S_NUM_VIDS;
919    dev->ops = &rtl8366_ops;
920    dev->devname = dev_name(smi->parent);
921
922    err = register_switch(dev, NULL);
923    if (err)
924        dev_err(smi->parent, "switch registration failed\n");
925
926    return err;
927}
928
929static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi)
930{
931    unregister_switch(&smi->sw_dev);
932}
933
934static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
935{
936    struct rtl8366_smi *smi = bus->priv;
937    u32 val = 0;
938    int err;
939
940    err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
941    if (err)
942        return 0xffff;
943
944    return val;
945}
946
947static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
948{
949    struct rtl8366_smi *smi = bus->priv;
950    u32 t;
951    int err;
952
953    err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
954    /* flush write */
955    (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
956
957    return err;
958}
959
960static int rtl8366s_mii_bus_match(struct mii_bus *bus)
961{
962    return (bus->read == rtl8366s_mii_read &&
963        bus->write == rtl8366s_mii_write);
964}
965
966static int rtl8366s_setup(struct rtl8366_smi *smi)
967{
968    int ret;
969
970    ret = rtl8366s_reset_chip(smi);
971    if (ret)
972        return ret;
973
974    ret = rtl8366s_hw_init(smi);
975    return ret;
976}
977
978static int rtl8366s_detect(struct rtl8366_smi *smi)
979{
980    u32 chip_id = 0;
981    u32 chip_ver = 0;
982    int ret;
983
984    ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
985    if (ret) {
986        dev_err(smi->parent, "unable to read chip id\n");
987        return ret;
988    }
989
990    switch (chip_id) {
991    case RTL8366S_CHIP_ID_8366:
992        break;
993    default:
994        dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
995        return -ENODEV;
996    }
997
998    ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
999                   &chip_ver);
1000    if (ret) {
1001        dev_err(smi->parent, "unable to read chip version\n");
1002        return ret;
1003    }
1004
1005    dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1006         chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1007
1008    return 0;
1009}
1010
1011static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1012    .detect = rtl8366s_detect,
1013    .setup = rtl8366s_setup,
1014
1015    .mii_read = rtl8366s_mii_read,
1016    .mii_write = rtl8366s_mii_write,
1017
1018    .get_vlan_mc = rtl8366s_get_vlan_mc,
1019    .set_vlan_mc = rtl8366s_set_vlan_mc,
1020    .get_vlan_4k = rtl8366s_get_vlan_4k,
1021    .set_vlan_4k = rtl8366s_set_vlan_4k,
1022    .get_mc_index = rtl8366s_get_mc_index,
1023    .set_mc_index = rtl8366s_set_mc_index,
1024    .get_mib_counter = rtl8366_get_mib_counter,
1025    .is_vlan_valid = rtl8366s_is_vlan_valid,
1026    .enable_vlan = rtl8366s_enable_vlan,
1027    .enable_vlan4k = rtl8366s_enable_vlan4k,
1028};
1029
1030static int __init rtl8366s_probe(struct platform_device *pdev)
1031{
1032    static int rtl8366_smi_version_printed;
1033    struct rtl8366s_platform_data *pdata;
1034    struct rtl8366_smi *smi;
1035    int err;
1036
1037    if (!rtl8366_smi_version_printed++)
1038        printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1039               " version " RTL8366S_DRIVER_VER"\n");
1040
1041    pdata = pdev->dev.platform_data;
1042    if (!pdata) {
1043        dev_err(&pdev->dev, "no platform data specified\n");
1044        err = -EINVAL;
1045        goto err_out;
1046    }
1047
1048    smi = rtl8366_smi_alloc(&pdev->dev);
1049    if (!smi) {
1050        err = -ENOMEM;
1051        goto err_out;
1052    }
1053
1054    smi->gpio_sda = pdata->gpio_sda;
1055    smi->gpio_sck = pdata->gpio_sck;
1056    smi->ops = &rtl8366s_smi_ops;
1057    smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1058    smi->num_ports = RTL8366S_NUM_PORTS;
1059    smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1060    smi->mib_counters = rtl8366s_mib_counters;
1061    smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1062
1063    err = rtl8366_smi_init(smi);
1064    if (err)
1065        goto err_free_smi;
1066
1067    platform_set_drvdata(pdev, smi);
1068
1069    err = rtl8366s_switch_init(smi);
1070    if (err)
1071        goto err_clear_drvdata;
1072
1073    return 0;
1074
1075 err_clear_drvdata:
1076    platform_set_drvdata(pdev, NULL);
1077    rtl8366_smi_cleanup(smi);
1078 err_free_smi:
1079    kfree(smi);
1080 err_out:
1081    return err;
1082}
1083
1084static int rtl8366s_phy_config_init(struct phy_device *phydev)
1085{
1086    if (!rtl8366s_mii_bus_match(phydev->bus))
1087        return -EINVAL;
1088
1089    return 0;
1090}
1091
1092static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1093{
1094    /* phy 4 might be connected to a second mac, allow aneg config */
1095    if (phydev->addr == RTL8366S_PHY_WAN)
1096        return genphy_config_aneg(phydev);
1097
1098    return 0;
1099}
1100
1101static struct phy_driver rtl8366s_phy_driver = {
1102    .phy_id = 0x001cc960,
1103    .name = "Realtek RTL8366S",
1104    .phy_id_mask = 0x1ffffff0,
1105    .features = PHY_GBIT_FEATURES,
1106    .config_aneg = rtl8366s_phy_config_aneg,
1107    .config_init = rtl8366s_phy_config_init,
1108    .read_status = genphy_read_status,
1109    .driver = {
1110        .owner = THIS_MODULE,
1111    },
1112};
1113
1114static int __devexit rtl8366s_remove(struct platform_device *pdev)
1115{
1116    struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1117
1118    if (smi) {
1119        rtl8366s_switch_cleanup(smi);
1120        platform_set_drvdata(pdev, NULL);
1121        rtl8366_smi_cleanup(smi);
1122        kfree(smi);
1123    }
1124
1125    return 0;
1126}
1127
1128static struct platform_driver rtl8366s_driver = {
1129    .driver = {
1130        .name = RTL8366S_DRIVER_NAME,
1131        .owner = THIS_MODULE,
1132    },
1133    .probe = rtl8366s_probe,
1134    .remove = __devexit_p(rtl8366s_remove),
1135};
1136
1137static int __init rtl8366s_module_init(void)
1138{
1139    int ret;
1140    ret = platform_driver_register(&rtl8366s_driver);
1141    if (ret)
1142        return ret;
1143
1144    ret = phy_driver_register(&rtl8366s_phy_driver);
1145    if (ret)
1146        goto err_platform_unregister;
1147
1148    return 0;
1149
1150 err_platform_unregister:
1151    platform_driver_unregister(&rtl8366s_driver);
1152    return ret;
1153}
1154module_init(rtl8366s_module_init);
1155
1156static void __exit rtl8366s_module_exit(void)
1157{
1158    phy_driver_unregister(&rtl8366s_phy_driver);
1159    platform_driver_unregister(&rtl8366s_driver);
1160}
1161module_exit(rtl8366s_module_exit);
1162
1163MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1164MODULE_VERSION(RTL8366S_DRIVER_VER);
1165MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1166MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1167MODULE_LICENSE("GPL v2");
1168MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
1169

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