| 1 | /* |
| 2 | * HND SiliconBackplane Gigabit Ethernet core registers |
| 3 | * |
| 4 | * Copyright 2007, Broadcom Corporation |
| 5 | * All Rights Reserved. |
| 6 | * |
| 7 | * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY |
| 8 | * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM |
| 9 | * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS |
| 10 | * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef _sbgige_h_ |
| 15 | #define _sbgige_h_ |
| 16 | |
| 17 | #include <typedefs.h> |
| 18 | #include <sbconfig.h> |
| 19 | #include <pcicfg.h> |
| 20 | |
| 21 | /* cpp contortions to concatenate w/arg prescan */ |
| 22 | #ifndef PAD |
| 23 | #define _PADLINE(line) pad ## line |
| 24 | #define _XSTR(line) _PADLINE(line) |
| 25 | #define PAD _XSTR(__LINE__) |
| 26 | #endif /* PAD */ |
| 27 | |
| 28 | /* PCI to OCP shim registers */ |
| 29 | typedef volatile struct { |
| 30 | uint32 FlushStatusControl; |
| 31 | uint32 FlushReadAddr; |
| 32 | uint32 FlushTimeoutCntr; |
| 33 | uint32 BarrierReg; |
| 34 | uint32 MaocpSIControl; |
| 35 | uint32 SiocpMaControl; |
| 36 | uint8 PAD[0x02E8]; |
| 37 | } sbgige_pcishim_t; |
| 38 | |
| 39 | /* SB core registers */ |
| 40 | typedef volatile struct { |
| 41 | /* PCI I/O Read/Write registers */ |
| 42 | uint8 pciio[0x0400]; |
| 43 | |
| 44 | /* Reserved */ |
| 45 | uint8 reserved[0x0400]; |
| 46 | |
| 47 | /* PCI configuration registers */ |
| 48 | pci_config_regs pcicfg; |
| 49 | uint8 PAD[0x0300]; |
| 50 | |
| 51 | /* PCI to OCP shim registers */ |
| 52 | sbgige_pcishim_t pcishim; |
| 53 | |
| 54 | /* Sonics SiliconBackplane registers */ |
| 55 | sbconfig_t sbconfig; |
| 56 | } sbgige_t; |
| 57 | |
| 58 | #endif /* _sbgige_h_ */ |
| 59 | |
