Root/package/ifxmips-dsl-api/patches/300-atm_compat.patch

1--- a/src/mei/ifxmips_atm_core.c
2+++ b/src/mei/ifxmips_atm_core.c
3@@ -58,9 +58,8 @@
4 /*
5  * Chip Specific Head File
6  */
7-#include <asm/ifx/ifx_types.h>
8-#include <asm/ifx/ifx_regs.h>
9-#include <asm/ifx/common_routines.h>
10+#include <ifxmips.h>
11+#include <ifxmips_cgu.h>
12 #include "ifxmips_atm_core.h"
13 
14 
15@@ -1146,7 +1145,7 @@ static INLINE void mailbox_signal(unsign
16 
17 static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
18 {
19- unsigned int qsb_clk = ifx_get_fpi_hz();
20+ unsigned int qsb_clk = ifxmips_get_fpi_hz();
21     unsigned int qsb_qid = queue + FIRST_QSB_QID;
22     union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
23     union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
24@@ -1318,7 +1317,7 @@ static void set_qsb(struct atm_vcc *vcc,
25 
26 static void qsb_global_set(void)
27 {
28- unsigned int qsb_clk = ifx_get_fpi_hz();
29+ unsigned int qsb_clk = ifxmips_get_fpi_hz();
30     int i;
31     unsigned int tmp1, tmp2, tmp3;
32 
33@@ -2505,3 +2504,4 @@ static void __exit ifx_atm_exit(void)
34 
35 module_init(ifx_atm_init);
36 module_exit(ifx_atm_exit);
37+MODULE_LICENSE("Dual BSD/GPL");
38--- a/src/mei/ifxmips_atm_ppe_common.h
39+++ b/src/mei/ifxmips_atm_ppe_common.h
40@@ -1,9 +1,10 @@
41 #ifndef IFXMIPS_ATM_PPE_COMMON_H
42 #define IFXMIPS_ATM_PPE_COMMON_H
43 
44-
45-
46-#if defined(CONFIG_DANUBE)
47+#if defined(CONFIG_IFXMIPS)
48+ #include "ifxmips_atm_ppe_danube.h"
49+ #define CONFIG_DANUBE
50+#elif defined(CONFIG_DANUBE)
51   #include "ifxmips_atm_ppe_danube.h"
52 #elif defined(CONFIG_AMAZON_SE)
53   #include "ifxmips_atm_ppe_amazon_se.h"
54@@ -16,7 +17,6 @@
55 #endif
56 
57 
58-
59 /*
60  * Code/Data Memory (CDM) Interface Configuration Register
61  */
62--- a/src/mei/ifxmips_atm_core.h
63+++ b/src/mei/ifxmips_atm_core.h
64@@ -25,8 +25,8 @@
65 #define IFXMIPS_ATM_CORE_H
66 
67 
68-
69-#include <asm/ifx/ifx_atm.h>
70+#include "ifxmips_compat.h"
71+#include "ifx_atm.h"
72 #include "ifxmips_atm_ppe_common.h"
73 #include "ifxmips_atm_fw_regs_common.h"
74 
75--- /dev/null
76+++ b/src/mei/ifxmips_compat.h
77@@ -0,0 +1,43 @@
78+#ifndef _IFXMIPS_COMPAT_H__
79+#define _IFXMIPS_COMPAT_H__
80+
81+#define IFX_SUCCESS 0
82+#define IFX_ERROR (-1)
83+
84+#define ATM_VBR_NRT ATM_VBR
85+#define ATM_VBR_RT 6
86+#define ATM_UBR_PLUS 7
87+#define ATM_GFR 8
88+
89+#define NUM_ENTITY(x) (sizeof(x) / sizeof(*(x)))
90+
91+#define SET_BITS(x, msb, lsb, value) \
92+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
93+
94+
95+#define IFX_PMU_ENABLE 1
96+#define IFX_PMU_DISABLE 0
97+
98+#define IFX_PMU_MODULE_DSL_DFE (1 << 9)
99+#define IFX_PMU_MODULE_AHBS (1 << 13)
100+#define IFX_PMU_MODULE_PPE_QSB (1 << 18)
101+#define IFX_PMU_MODULE_PPE_SLL01 (1 << 19)
102+#define IFX_PMU_MODULE_PPE_TC (1 << 21)
103+#define IFX_PMU_MODULE_PPE_EMA (1 << 22)
104+#define IFX_PMU_MODULE_PPE_TOP (1 << 29)
105+
106+#define ifx_pmu_set(a,b) {if(a == IFX_PMU_ENABLE) ifxmips_pmu_enable(b); else ifxmips_pmu_disable(b);}
107+
108+#define PPE_TOP_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x))
109+#define PPE_SLL01_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_SLL01, (__x))
110+#define PPE_TC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TC, (__x))
111+#define PPE_EMA_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_EMA, (__x))
112+#define PPE_QSB_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_QSB, (__x))
113+#define PPE_TPE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHBS, (__x))
114+#define DSL_DFE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DSL_DFE, (__x))
115+
116+#define IFX_REG_W32(_v, _r) __raw_writel((_v), (_r))
117+
118+#define CONFIG_IFXMIPS_DSL_CPE_MEI y
119+
120+#endif
121--- a/src/mei/ifxmips_atm_ppe_danube.h
122+++ b/src/mei/ifxmips_atm_ppe_danube.h
123@@ -1,7 +1,7 @@
124 #ifndef IFXMIPS_ATM_PPE_DANUBE_H
125 #define IFXMIPS_ATM_PPE_DANUBE_H
126 
127-
128+#include <ifxmips_irq.h>
129 
130 /*
131  * FPI Configuration Bus Register and Memory Address Mapping
132@@ -93,7 +93,7 @@
133 /*
134  * Mailbox IGU1 Interrupt
135  */
136-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
137+#define PPE_MAILBOX_IGU1_INT IFXMIPS_PPE_MBOX_INT
138 
139 
140 
141--- a/src/mei/ifxmips_atm_danube.c
142+++ b/src/mei/ifxmips_atm_danube.c
143@@ -45,10 +45,9 @@
144 /*
145  * Chip Specific Head File
146  */
147-#include <asm/ifx/ifx_types.h>
148-#include <asm/ifx/ifx_regs.h>
149-#include <asm/ifx/common_routines.h>
150-#include <asm/ifx/ifx_pmu.h>
151+#include <ifxmips.h>
152+#include <ifxmips_pmu.h>
153+#include "ifxmips_compat.h"
154 #include "ifxmips_atm_core.h"
155 #include "ifxmips_atm_fw_danube.h"
156 
157

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