| 1 | --- a/ath/if_ath.c |
| 2 | +++ b/ath/if_ath.c |
| 3 | @@ -606,6 +606,14 @@ ath_attach(u_int16_t devid, struct net_d |
| 4 | } |
| 5 | sc->sc_ah = ah; |
| 6 | |
| 7 | + /* WAR for AR7100 PCI bug */ |
| 8 | +#ifdef CONFIG_ATHEROS_AR71XX |
| 9 | + if ((ar_device(sc->devid) >= 5210) && (ar_device(sc->devid) < 5416)) { |
| 10 | + ath_hal_setcapability(ah, HAL_CAP_DMABURST_RX, 0, HAL_DMABURST_4B, NULL); |
| 11 | + ath_hal_setcapability(ah, HAL_CAP_DMABURST_TX, 0, HAL_DMABURST_4B, NULL); |
| 12 | + } |
| 13 | +#endif |
| 14 | + |
| 15 | /* |
| 16 | * Check if the MAC has multi-rate retry support. |
| 17 | * We do this by trying to setup a fake extended |
| 18 | @@ -7568,7 +7576,7 @@ ath_txq_setup(struct ath_softc *sc, int |
| 19 | if (qtype == HAL_TX_QUEUE_UAPSD) |
| 20 | qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; |
| 21 | else |
| 22 | - qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | |
| 23 | + qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXOKINT_ENABLE | |
| 24 | HAL_TXQ_TXDESCINT_ENABLE; |
| 25 | qnum = ath_hal_setuptxqueue(ah, qtype, &qi); |
| 26 | if (qnum == -1) { |
| 27 | --- a/ath_hal/ah_os.c |
| 28 | +++ b/ath_hal/ah_os.c |
| 29 | @@ -126,6 +126,13 @@ ath_hal_printf(struct ath_hal *ah, const |
| 30 | } |
| 31 | EXPORT_SYMBOL(ath_hal_printf); |
| 32 | |
| 33 | +void __ahdecl |
| 34 | +ath_hal_printstr(struct ath_hal *ah, const char *str) |
| 35 | +{ |
| 36 | + printk("%s", str); |
| 37 | +} |
| 38 | +EXPORT_SYMBOL(ath_hal_printstr); |
| 39 | + |
| 40 | /* |
| 41 | * Format an Ethernet MAC for printing. |
| 42 | */ |
| 43 | --- a/ath_hal/ah_os.h |
| 44 | +++ b/ath_hal/ah_os.h |
| 45 | @@ -156,69 +156,23 @@ extern u_int32_t __ahdecl ath_hal_getupt |
| 46 | #endif |
| 47 | #endif /* AH_BYTE_ORDER */ |
| 48 | |
| 49 | -/* |
| 50 | - * Some big-endian architectures don't set CONFIG_GENERIC_IOMAP, but fail to |
| 51 | - * implement iowrite32be and ioread32be. Provide compatibility macros when |
| 52 | - * it's needed. |
| 53 | - * |
| 54 | - * As of Linux 2.6.24, only MIPS, PARISC and PowerPC implement iowrite32be and |
| 55 | - * ioread32be as functions. |
| 56 | - * |
| 57 | - * The downside or the replacement macros it that we may be byte-swapping data |
| 58 | - * for the second time, so the native implementations should be preferred. |
| 59 | - */ |
| 60 | -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)) && \ |
| 61 | - !defined(CONFIG_GENERIC_IOMAP) && (AH_BYTE_ORDER == AH_BIG_ENDIAN) && \ |
| 62 | - !defined(__mips__) && !defined(__hppa__) && !defined(__powerpc__) |
| 63 | -# ifndef iowrite32be |
| 64 | -# define iowrite32be(_val, _addr) iowrite32(swab32((_val)), (_addr)) |
| 65 | -# endif |
| 66 | -# ifndef ioread32be |
| 67 | -# define ioread32be(_addr) swab32(ioread32((_addr))) |
| 68 | -# endif |
| 69 | -#endif |
| 70 | +#define IS_SWAPPED(_ah, _reg) \ |
| 71 | + ((_ah)->ah_swapped && \ |
| 72 | + (((0x4000 <= (_reg)) && ((_reg) < 0x5000)) || \ |
| 73 | + ((0x7000 <= (_reg)) && ((_reg) < 0x8000)))) |
| 74 | + |
| 75 | +#define SWAPREG(_ah, _reg, _val) \ |
| 76 | + (IS_SWAPPED(_ah, _reg) ? cpu_to_le32(_val) : (_val)) |
| 77 | |
| 78 | /* |
| 79 | * The register accesses are done using target-specific functions when |
| 80 | * debugging is enabled (AH_DEBUG) or it's explicitly requested for the target. |
| 81 | - * |
| 82 | - * The hardware registers use little-endian byte order natively. Big-endian |
| 83 | - * systems are configured by HAL to enable hardware byte-swap of register reads |
| 84 | - * and writes at reset. This avoid the need to byte-swap the data in software. |
| 85 | - * However, the registers in a certain area from 0x4000 to 0x4fff (PCI clock |
| 86 | - * domain registers) are not byte swapped! |
| 87 | - * |
| 88 | - * Since Linux I/O primitives default to little-endian operations, we only |
| 89 | - * need to suppress byte-swapping on big-endian systems outside the area used |
| 90 | - * by the PCI clock domain registers. |
| 91 | */ |
| 92 | -#if (AH_BYTE_ORDER == AH_BIG_ENDIAN) |
| 93 | -#define is_reg_le(__reg) ((0x4000 <= (__reg) && (__reg) < 0x5000)) |
| 94 | -#else |
| 95 | -#define is_reg_le(__reg) 1 |
| 96 | -#endif |
| 97 | - |
| 98 | -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12) |
| 99 | -#define _OS_REG_WRITE(_ah, _reg, _val) do { \ |
| 100 | - is_reg_le(_reg) ? \ |
| 101 | - iowrite32((_val), (_ah)->ah_sh + (_reg)) : \ |
| 102 | - iowrite32be((_val), (_ah)->ah_sh + (_reg)); \ |
| 103 | - } while (0) |
| 104 | -#define _OS_REG_READ(_ah, _reg) \ |
| 105 | - (is_reg_le(_reg) ? \ |
| 106 | - ioread32((_ah)->ah_sh + (_reg)) : \ |
| 107 | - ioread32be((_ah)->ah_sh + (_reg))) |
| 108 | -#else |
| 109 | #define _OS_REG_WRITE(_ah, _reg, _val) do { \ |
| 110 | - writel(is_reg_le(_reg) ? \ |
| 111 | - (_val) : cpu_to_le32(_val), \ |
| 112 | - (_ah)->ah_sh + (_reg)); \ |
| 113 | - } while (0) |
| 114 | + __raw_writel(SWAPREG(_ah, _reg, _val), (_ah)->ah_sh + (_reg)); \ |
| 115 | +} while (0) |
| 116 | #define _OS_REG_READ(_ah, _reg) \ |
| 117 | - (is_reg_le(_reg) ? \ |
| 118 | - readl((_ah)->ah_sh + (_reg)) : \ |
| 119 | - cpu_to_le32(readl((_ah)->ah_sh + (_reg)))) |
| 120 | -#endif /* KERNEL_VERSION(2,6,12) */ |
| 121 | + SWAPREG(_ah, _reg, __raw_readl((_ah)->ah_sh + (_reg))) |
| 122 | |
| 123 | /* |
| 124 | * The functions in this section are not intended to be invoked by MadWifi |
| 125 | --- a/ath/if_ath_hal.h |
| 126 | +++ b/ath/if_ath_hal.h |
| 127 | @@ -778,17 +778,6 @@ static inline HAL_STATUS ath_hal_getcapa |
| 128 | return ret; |
| 129 | } |
| 130 | |
| 131 | -static inline HAL_BOOL ath_hal_radar_wait(struct ath_hal *ah, HAL_CHANNEL *a1) |
| 132 | -{ |
| 133 | - HAL_BOOL ret; |
| 134 | - ATH_HAL_LOCK_IRQ(ah->ah_sc); |
| 135 | - ath_hal_set_function(__func__); |
| 136 | - ret = ah->ah_radarWait(ah, a1); |
| 137 | - ath_hal_set_function(NULL); |
| 138 | - ATH_HAL_UNLOCK_IRQ(ah->ah_sc); |
| 139 | - return ret; |
| 140 | -} |
| 141 | - |
| 142 | static inline HAL_BOOL ath_hal_setmcastfilterindex(struct ath_hal *ah, |
| 143 | u_int32_t index) |
| 144 | { |
| 145 | @@ -1268,8 +1257,6 @@ static inline void ath_hal_dump_map(stru |
| 146 | /* HAL_STATUS ah_getCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE a1, u_int32_t capability, u_int32_t *result) */ |
| 147 | __print_symbol("%s=ah_getCapability\n", |
| 148 | (unsigned long)ah->ah_getCapability); |
| 149 | - /* HAL_BOOL ah_radarWait(struct ath_hal *ah, HAL_CHANNEL *a1) */ |
| 150 | - __print_symbol("%s=ah_radarWait\n", (unsigned long)ah->ah_radarWait); |
| 151 | /* HAL_BOOL ah_setMulticastFilterIndex(struct ath_hal *ah, u_int32_t index) */ |
| 152 | __print_symbol("%s=ah_setMulticastFilterIndex\n", |
| 153 | (unsigned long)ah->ah_setMulticastFilterIndex); |
| 154 | |
