| 1 | --- a/ath/if_ath.c |
| 2 | +++ b/ath/if_ath.c |
| 3 | @@ -2308,6 +2308,17 @@ ath_intr(int irq, void *dev_id, struct p |
| 4 | |
| 5 | sc->sc_isr = status; |
| 6 | status &= sc->sc_imask; /* discard unasked for bits */ |
| 7 | + |
| 8 | + /* Treat RXORN as non-fatal. Either the bus is busy or the CPU |
| 9 | + * is not fast enough to process all frames. Treat it like |
| 10 | + * an Rx interrupt |
| 11 | + */ |
| 12 | + if (status & HAL_INT_RXORN) { |
| 13 | + sc->sc_stats.ast_rxorn++; |
| 14 | + status &= ~HAL_INT_RXORN; |
| 15 | + status |= HAL_INT_RX; |
| 16 | + } |
| 17 | + |
| 18 | /* As soon as we know we have a real interrupt we intend to service, |
| 19 | * we will check to see if we need an initial hardware TSF reading. |
| 20 | * Normally we would just populate this all the time to keep things |
| 21 | @@ -2320,10 +2331,6 @@ ath_intr(int irq, void *dev_id, struct p |
| 22 | sc->sc_stats.ast_hardware++; |
| 23 | ath_hal_intrset(ah, 0); /* disable intr's until reset */ |
| 24 | ATH_SCHEDULE_TQUEUE(&sc->sc_fataltq, &needmark); |
| 25 | - } else if (status & HAL_INT_RXORN) { |
| 26 | - sc->sc_stats.ast_rxorn++; |
| 27 | - ath_hal_intrset(ah, 0); /* disable intr's until reset */ |
| 28 | - ATH_SCHEDULE_TQUEUE(&sc->sc_rxorntq, &needmark); |
| 29 | } else { |
| 30 | if (status & HAL_INT_SWBA) { |
| 31 | struct ieee80211vap * vap; |
| 32 | |
