| 1 | --- a/net80211/ieee80211_rate.h |
| 2 | +++ b/net80211/ieee80211_rate.h |
| 3 | @@ -81,6 +81,8 @@ struct ieee80211vap; |
| 4 | |
| 5 | /* Multi-rare retry: 3 additional rate/retry pairs */ |
| 6 | struct ieee80211_mrr { |
| 7 | + int rate0; |
| 8 | + int retries0; |
| 9 | int rate1; |
| 10 | int retries1; |
| 11 | int rate2; |
| 12 | @@ -142,7 +144,7 @@ struct ieee80211_rate_ops { |
| 13 | * for packets that were successfully sent and for those that |
| 14 | * failed (consult the descriptor for details). */ |
| 15 | void (*tx_complete)(struct ath_softc *sc, struct ath_node *an, |
| 16 | - const struct ath_buf *bf); |
| 17 | + const struct ath_buf *bf, const struct ieee80211_mrr *mrr); |
| 18 | }; |
| 19 | |
| 20 | struct ath_ratectrl { |
| 21 | --- a/ath/if_ath.c |
| 22 | +++ b/ath/if_ath.c |
| 23 | @@ -8638,6 +8638,8 @@ ath_tx_processq(struct ath_softc *sc, st |
| 24 | |
| 25 | ni = bf->bf_node; |
| 26 | if (ni != NULL) { |
| 27 | + struct ieee80211_mrr mrr; |
| 28 | + |
| 29 | an = ATH_NODE(ni); |
| 30 | if (ts->ts_status == 0) { |
| 31 | u_int8_t txant = ts->ts_antenna; |
| 32 | @@ -8690,15 +8692,43 @@ ath_tx_processq(struct ath_softc *sc, st |
| 33 | lr = ts->ts_longretry; |
| 34 | sc->sc_stats.ast_tx_shortretry += sr; |
| 35 | sc->sc_stats.ast_tx_longretry += lr; |
| 36 | + memset(&mrr, 0, sizeof(mrr)); |
| 37 | + |
| 38 | + switch(ah->ah_macType) { |
| 39 | + case 5210: |
| 40 | + case 5211: |
| 41 | + goto skip_mrr; |
| 42 | + |
| 43 | + case 5212: |
| 44 | + mrr.rate0 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate0)].ieeerate; |
| 45 | + mrr.rate1 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate1)].ieeerate; |
| 46 | + mrr.rate2 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate2)].ieeerate; |
| 47 | + mrr.rate3 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate3)].ieeerate; |
| 48 | + break; |
| 49 | + |
| 50 | + case 5416: |
| 51 | + mrr.rate0 = sc->sc_hwmap[MS(ds->ds_ctl3, AR5416_XmitRate0)].ieeerate; |
| 52 | + mrr.rate1 = sc->sc_hwmap[MS(ds->ds_ctl3, AR5416_XmitRate1)].ieeerate; |
| 53 | + mrr.rate2 = sc->sc_hwmap[MS(ds->ds_ctl3, AR5416_XmitRate2)].ieeerate; |
| 54 | + mrr.rate3 = sc->sc_hwmap[MS(ds->ds_ctl3, AR5416_XmitRate3)].ieeerate; |
| 55 | + break; |
| 56 | + } |
| 57 | + |
| 58 | + mrr.retries0 = MS(ds->ds_ctl2, AR_XmitDataTries0); |
| 59 | + mrr.retries1 = MS(ds->ds_ctl2, AR_XmitDataTries1); |
| 60 | + mrr.retries2 = MS(ds->ds_ctl2, AR_XmitDataTries2); |
| 61 | + mrr.retries3 = MS(ds->ds_ctl2, AR_XmitDataTries3); |
| 62 | + |
| 63 | /* |
| 64 | * Hand the descriptor to the rate control algorithm |
| 65 | * if the frame wasn't dropped for filtering or sent |
| 66 | * w/o waiting for an ack. In those cases the rssi |
| 67 | * and retry counts will be meaningless. |
| 68 | */ |
| 69 | +skip_mrr: |
| 70 | if ((ts->ts_status & HAL_TXERR_FILT) == 0 && |
| 71 | (bf->bf_flags & HAL_TXDESC_NOACK) == 0) |
| 72 | - sc->sc_rc->ops->tx_complete(sc, an, bf); |
| 73 | + sc->sc_rc->ops->tx_complete(sc, an, bf, &mrr); |
| 74 | } |
| 75 | |
| 76 | bus_unmap_single(sc->sc_bdev, bf->bf_skbaddr, |
| 77 | --- a/ath/if_athvar.h |
| 78 | +++ b/ath/if_athvar.h |
| 79 | @@ -595,6 +595,46 @@ struct ath_vap { |
| 80 | (_tqs)->axq_link = NULL; \ |
| 81 | } while (0) |
| 82 | |
| 83 | +/* |
| 84 | + * Definitions for pulling the rate and trie counts from |
| 85 | + * a 5212 h/w descriptor. These Don't belong here; the |
| 86 | + * driver should record this information so the rate control |
| 87 | + * code doesn't go groveling around in the descriptor bits. |
| 88 | + */ |
| 89 | +#define ds_ctl2 ds_hw[0] |
| 90 | +#define ds_ctl3 ds_hw[1] |
| 91 | + |
| 92 | +/* TX ds_ctl3 */ |
| 93 | +#define AR_XmitDataTries0 0x000f0000 /* series 0 max attempts */ |
| 94 | +#define AR_XmitDataTries0_S 16 |
| 95 | +#define AR_XmitDataTries1 0x00f00000 /* series 1 max attempts */ |
| 96 | +#define AR_XmitDataTries1_S 20 |
| 97 | +#define AR_XmitDataTries2 0x0f000000 /* series 2 max attempts */ |
| 98 | +#define AR_XmitDataTries2_S 24 |
| 99 | +#define AR_XmitDataTries3 0xf0000000 /* series 3 max attempts */ |
| 100 | +#define AR_XmitDataTries3_S 28 |
| 101 | + |
| 102 | +/* TX ds_ctl3 */ |
| 103 | +#define AR_XmitRate0 0x0000001f /* series 0 tx rate */ |
| 104 | +#define AR_XmitRate0_S 0 |
| 105 | +#define AR_XmitRate1 0x000003e0 /* series 1 tx rate */ |
| 106 | +#define AR_XmitRate1_S 5 |
| 107 | +#define AR_XmitRate2 0x00007c00 /* series 2 tx rate */ |
| 108 | +#define AR_XmitRate2_S 10 |
| 109 | +#define AR_XmitRate3 0x000f8000 /* series 3 tx rate */ |
| 110 | +#define AR_XmitRate3_S 15 |
| 111 | + |
| 112 | +#define AR5416_XmitRate0 0x000000ff |
| 113 | +#define AR5416_XmitRate0_S 0 |
| 114 | +#define AR5416_XmitRate1 0x0000ff00 |
| 115 | +#define AR5416_XmitRate1_S 8 |
| 116 | +#define AR5416_XmitRate2 0x00ff0000 |
| 117 | +#define AR5416_XmitRate2_S 16 |
| 118 | +#define AR5416_XmitRate3 0xff000000 |
| 119 | +#define AR5416_XmitRate3_S 24 |
| 120 | + |
| 121 | +#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) |
| 122 | + |
| 123 | /* |
| 124 | * concat buffers from one queue to other |
| 125 | */ |
| 126 | --- a/ath_rate/amrr/amrr.c |
| 127 | +++ b/ath_rate/amrr/amrr.c |
| 128 | @@ -123,7 +123,8 @@ ath_rate_get_mrr(struct ath_softc *sc, s |
| 129 | |
| 130 | static void |
| 131 | ath_rate_tx_complete(struct ath_softc *sc, |
| 132 | - struct ath_node *an, const struct ath_buf *bf) |
| 133 | + struct ath_node *an, const struct ath_buf *bf, |
| 134 | + const struct ieee80211_mrr *mrr) |
| 135 | { |
| 136 | struct amrr_node *amn = ATH_NODE_AMRR(an); |
| 137 | const struct ath_tx_status *ts = &bf->bf_dsstatus.ds_txstat; |
| 138 | --- a/ath_rate/minstrel/minstrel.c |
| 139 | +++ b/ath_rate/minstrel/minstrel.c |
| 140 | @@ -333,7 +333,8 @@ ath_rate_get_mrr(struct ath_softc *sc, s |
| 141 | |
| 142 | static void |
| 143 | ath_rate_tx_complete(struct ath_softc *sc, |
| 144 | - struct ath_node *an, const struct ath_buf *bf) |
| 145 | + struct ath_node *an, const struct ath_buf *bf, |
| 146 | + const struct ieee80211_mrr *mrr) |
| 147 | { |
| 148 | struct minstrel_node *sn = ATH_NODE_MINSTREL(an); |
| 149 | struct ieee80211com *ic = &sc->sc_ic; |
| 150 | @@ -341,12 +342,9 @@ ath_rate_tx_complete(struct ath_softc *s |
| 151 | const struct ath_desc *ds = &bf->bf_desc[0]; |
| 152 | int final_rate = 0; |
| 153 | int tries = 0; |
| 154 | - int mrr; |
| 155 | + int use_mrr; |
| 156 | int final_ndx; |
| 157 | - int rate0, tries0, ndx0; |
| 158 | - int rate1, tries1, ndx1; |
| 159 | - int rate2, tries2, ndx2; |
| 160 | - int rate3, tries3, ndx3; |
| 161 | + int ndx0, ndx1, ndx2, ndx3; |
| 162 | |
| 163 | /* This is the index in the retry chain we finish at. |
| 164 | * With no retransmits, it is always 0. |
| 165 | @@ -376,9 +374,9 @@ ath_rate_tx_complete(struct ath_softc *s |
| 166 | if (!ts->ts_status) /* Success when sending a packet*/ |
| 167 | sn->rs_ratesuccess[final_ndx]++; |
| 168 | |
| 169 | - mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT) && ENABLE_MRR; |
| 170 | + use_mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT) && ENABLE_MRR; |
| 171 | |
| 172 | - if (!mrr) { |
| 173 | + if (!use_mrr) { |
| 174 | if ((0 <= final_ndx) && (final_ndx < sn->num_rates)) { |
| 175 | sn->rs_rateattempts[final_ndx] += tries; /* only one rate was used */ |
| 176 | } |
| 177 | @@ -388,47 +386,36 @@ ath_rate_tx_complete(struct ath_softc *s |
| 178 | /* Now, query the hal/hardware to find out the contents of the multirate retry chain. |
| 179 | * If we have it set to 6,3,2,2, this call will always return 6,3,2,2. For some packets, we can |
| 180 | * get a mrr of 0, -1, -1, -1, which indicates there is no chain installed for that packet */ |
| 181 | - rate0 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate0)].ieeerate; |
| 182 | - tries0 = MS(ds->ds_ctl2, AR_XmitDataTries0); |
| 183 | - ndx0 = rate_to_ndx(sn, rate0); |
| 184 | + ndx0 = rate_to_ndx(sn, mrr->rate0); |
| 185 | + ndx1 = rate_to_ndx(sn, mrr->rate1); |
| 186 | + ndx2 = rate_to_ndx(sn, mrr->rate2); |
| 187 | + ndx3 = rate_to_ndx(sn, mrr->rate3); |
| 188 | |
| 189 | - rate1 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate1)].ieeerate; |
| 190 | - tries1 = MS(ds->ds_ctl2, AR_XmitDataTries1); |
| 191 | - ndx1 = rate_to_ndx(sn, rate1); |
| 192 | - |
| 193 | - rate2 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate2)].ieeerate; |
| 194 | - tries2 = MS(ds->ds_ctl2, AR_XmitDataTries2); |
| 195 | - ndx2 = rate_to_ndx(sn, rate2); |
| 196 | - |
| 197 | - rate3 = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate3)].ieeerate; |
| 198 | - tries3 = MS(ds->ds_ctl2, AR_XmitDataTries3); |
| 199 | - ndx3 = rate_to_ndx(sn, rate3); |
| 200 | - |
| 201 | - sn->rs_rateattempts[ndx0] += MIN(tries, tries0); |
| 202 | - if (tries <= tries0) |
| 203 | + sn->rs_rateattempts[ndx0] += MIN(tries, mrr->retries0); |
| 204 | + if (tries <= mrr->retries0) |
| 205 | return; |
| 206 | |
| 207 | - if (tries1 < 0) |
| 208 | + if (mrr->retries1 < 0) |
| 209 | return; |
| 210 | - tries = tries - tries0; |
| 211 | - sn->rs_rateattempts[ndx1] += MIN(tries, tries1); |
| 212 | - if (tries <= tries1) |
| 213 | + tries = tries - mrr->retries0; |
| 214 | + sn->rs_rateattempts[ndx1] += MIN(tries, mrr->retries1); |
| 215 | + if (tries <= mrr->retries1) |
| 216 | return; |
| 217 | |
| 218 | if (bf->rcflags) |
| 219 | sn->sample_count++; |
| 220 | |
| 221 | - if (tries2 < 0) |
| 222 | + if (mrr->retries2 < 0) |
| 223 | return; |
| 224 | - tries = tries - tries1; |
| 225 | - sn->rs_rateattempts[ndx2] += MIN(tries, tries2); |
| 226 | - if (tries <= tries2) |
| 227 | + tries = tries - mrr->retries1; |
| 228 | + sn->rs_rateattempts[ndx2] += MIN(tries, mrr->retries2); |
| 229 | + if (tries <= mrr->retries2) |
| 230 | return; |
| 231 | |
| 232 | - if (tries3 < 0) |
| 233 | + if (mrr->retries3 < 0) |
| 234 | return; |
| 235 | - tries = tries - tries2; |
| 236 | - sn->rs_rateattempts[ndx3] += MIN(tries, tries3); |
| 237 | + tries = tries - mrr->retries2; |
| 238 | + sn->rs_rateattempts[ndx3] += MIN(tries, mrr->retries3); |
| 239 | } |
| 240 | |
| 241 | static void |
| 242 | --- a/ath_rate/minstrel/minstrel.h |
| 243 | +++ b/ath_rate/minstrel/minstrel.h |
| 244 | @@ -172,36 +172,6 @@ struct minstrel_node { |
| 245 | |
| 246 | #define ATH_NODE_MINSTREL(an) ((struct minstrel_node *)&an[1]) |
| 247 | |
| 248 | -/* |
| 249 | - * Definitions for pulling the rate and trie counts from |
| 250 | - * a 5212 h/w descriptor. These Don't belong here; the |
| 251 | - * driver should record this information so the rate control |
| 252 | - * code doesn't go groveling around in the descriptor bits. |
| 253 | - */ |
| 254 | -#define ds_ctl2 ds_hw[0] |
| 255 | -#define ds_ctl3 ds_hw[1] |
| 256 | - |
| 257 | -/* TX ds_ctl3 */ |
| 258 | -#define AR_XmitDataTries0 0x000f0000 /* series 0 max attempts */ |
| 259 | -#define AR_XmitDataTries0_S 16 |
| 260 | -#define AR_XmitDataTries1 0x00f00000 /* series 1 max attempts */ |
| 261 | -#define AR_XmitDataTries1_S 20 |
| 262 | -#define AR_XmitDataTries2 0x0f000000 /* series 2 max attempts */ |
| 263 | -#define AR_XmitDataTries2_S 24 |
| 264 | -#define AR_XmitDataTries3 0xf0000000 /* series 3 max attempts */ |
| 265 | -#define AR_XmitDataTries3_S 28 |
| 266 | - |
| 267 | -/* TX ds_ctl3 */ |
| 268 | -#define AR_XmitRate0 0x0000001f /* series 0 tx rate */ |
| 269 | -#define AR_XmitRate0_S 0 |
| 270 | -#define AR_XmitRate1 0x000003e0 /* series 1 tx rate */ |
| 271 | -#define AR_XmitRate1_S 5 |
| 272 | -#define AR_XmitRate2 0x00007c00 /* series 2 tx rate */ |
| 273 | -#define AR_XmitRate2_S 10 |
| 274 | -#define AR_XmitRate3 0x000f8000 /* series 3 tx rate */ |
| 275 | -#define AR_XmitRate3_S 15 |
| 276 | - |
| 277 | -#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) |
| 278 | #endif /* _DEV_ATH_RATE_MINSTEL_H */ |
| 279 | |
| 280 | /* The comment below is magic for those who use emacs to edit this file. */ |
| 281 | --- a/ath_rate/onoe/onoe.c |
| 282 | +++ b/ath_rate/onoe/onoe.c |
| 283 | @@ -137,7 +137,8 @@ ath_rate_get_mrr(struct ath_softc *sc, s |
| 284 | |
| 285 | static void |
| 286 | ath_rate_tx_complete(struct ath_softc *sc, |
| 287 | - struct ath_node *an, const struct ath_buf *bf) |
| 288 | + struct ath_node *an, const struct ath_buf *bf, |
| 289 | + const struct ieee80211_mrr *mrr) |
| 290 | { |
| 291 | struct onoe_node *on = ATH_NODE_ONOE(an); |
| 292 | const struct ath_tx_status *ts = &bf->bf_dsstatus.ds_txstat; |
| 293 | --- a/ath_rate/sample/sample.c |
| 294 | +++ b/ath_rate/sample/sample.c |
| 295 | @@ -178,10 +178,6 @@ static __inline int best_rate_ndx(struct |
| 296 | !sn->stats[size_bin][x].packets_acked)) |
| 297 | continue; |
| 298 | |
| 299 | - /* 9 megabits never works better than 12 */ |
| 300 | - if (sn->rates[x].rate == 18) |
| 301 | - continue; |
| 302 | - |
| 303 | /* don't use a bit-rate that has been failing */ |
| 304 | if (sn->stats[size_bin][x].successive_failures > 3) |
| 305 | continue; |
| 306 | @@ -234,10 +230,6 @@ pick_sample_ndx(struct sample_node *sn, |
| 307 | if (sn->rates[ndx].rate > 22 && ndx > current_ndx + 2) |
| 308 | continue; |
| 309 | |
| 310 | - /* 9 megabits never works better than 12 */ |
| 311 | - if (sn->rates[ndx].rate == 18) |
| 312 | - continue; |
| 313 | - |
| 314 | /* if we're using 11 megabits, only sample up to 12 megabits |
| 315 | */ |
| 316 | if (sn->rates[current_ndx].rate == 22 && ndx > current_ndx + 1) |
| 317 | @@ -531,7 +523,8 @@ update_stats(struct ath_softc *sc, struc |
| 318 | |
| 319 | static void |
| 320 | ath_rate_tx_complete(struct ath_softc *sc, |
| 321 | - struct ath_node *an, const struct ath_buf *bf) |
| 322 | + struct ath_node *an, const struct ath_buf *bf, |
| 323 | + const struct ieee80211_mrr *mrr) |
| 324 | { |
| 325 | struct sample_node *sn = ATH_NODE_SAMPLE(an); |
| 326 | struct ieee80211com *ic = &sc->sc_ic; |
| 327 | @@ -541,7 +534,7 @@ ath_rate_tx_complete(struct ath_softc *s |
| 328 | unsigned int short_tries; |
| 329 | unsigned int long_tries; |
| 330 | unsigned int frame_size; |
| 331 | - unsigned int mrr; |
| 332 | + unsigned int use_mrr; |
| 333 | |
| 334 | final_rate = sc->sc_hwmap[ts->ts_rate &~ HAL_TXSTAT_ALTRATE].ieeerate; |
| 335 | short_tries = ts->ts_shortretry + 1; |
| 336 | @@ -557,7 +550,7 @@ ath_rate_tx_complete(struct ath_softc *s |
| 337 | return; |
| 338 | } |
| 339 | |
| 340 | - mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT) && ENABLE_MRR; |
| 341 | + use_mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT) && ENABLE_MRR; |
| 342 | |
| 343 | |
| 344 | if (sc->sc_mrretry && ts->ts_status) { |
| 345 | @@ -566,22 +559,15 @@ ath_rate_tx_complete(struct ath_softc *s |
| 346 | dev_info, |
| 347 | MAC_ADDR(an->an_node.ni_macaddr), |
| 348 | bin_to_size(size_to_bin(frame_size)), |
| 349 | - sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate0)].ieeerate, |
| 350 | - MS(ds->ds_ctl2, AR_XmitDataTries0), |
| 351 | - sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate1)].ieeerate, |
| 352 | - MS(ds->ds_ctl2, AR_XmitDataTries1), |
| 353 | - sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate2)].ieeerate, |
| 354 | - MS(ds->ds_ctl2, AR_XmitDataTries2), |
| 355 | - sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate3)].ieeerate, |
| 356 | - MS(ds->ds_ctl2, AR_XmitDataTries3), |
| 357 | + mrr->rate0, |
| 358 | + mrr->rate1, |
| 359 | + mrr->rate2, |
| 360 | + mrr->rate3, |
| 361 | ts->ts_status ? "FAIL" : "OK", |
| 362 | short_tries, long_tries); |
| 363 | } |
| 364 | |
| 365 | - mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT) && ENABLE_MRR; |
| 366 | - |
| 367 | - |
| 368 | - if (!mrr || !(ts->ts_rate & HAL_TXSTAT_ALTRATE)) { |
| 369 | + if (!use_mrr || !(ts->ts_rate & HAL_TXSTAT_ALTRATE)) { |
| 370 | /* only one rate was used */ |
| 371 | int ndx = rate_to_ndx(sn, final_rate); |
| 372 | if ((ndx >= 0) && (ndx < sn->num_rates)) { |
| 373 | @@ -593,7 +579,6 @@ ath_rate_tx_complete(struct ath_softc *s |
| 374 | short_tries, long_tries, ts->ts_status); |
| 375 | } |
| 376 | } else { |
| 377 | - unsigned int rate[4], tries[4]; |
| 378 | int ndx[4]; |
| 379 | int finalTSIdx = ts->ts_finaltsi; |
| 380 | |
| 381 | @@ -601,21 +586,10 @@ ath_rate_tx_complete(struct ath_softc *s |
| 382 | * Process intermediate rates that failed. |
| 383 | */ |
| 384 | |
| 385 | - rate[0] = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate0)].ieeerate; |
| 386 | - tries[0] = MS(ds->ds_ctl2, AR_XmitDataTries0); |
| 387 | - ndx[0] = rate_to_ndx(sn, rate[0]); |
| 388 | - |
| 389 | - rate[1] = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate1)].ieeerate; |
| 390 | - tries[1] = MS(ds->ds_ctl2, AR_XmitDataTries1); |
| 391 | - ndx[1] = rate_to_ndx(sn, rate[1]); |
| 392 | - |
| 393 | - rate[2] = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate2)].ieeerate; |
| 394 | - tries[2] = MS(ds->ds_ctl2, AR_XmitDataTries2); |
| 395 | - ndx[2] = rate_to_ndx(sn, rate[2]); |
| 396 | - |
| 397 | - rate[3] = sc->sc_hwmap[MS(ds->ds_ctl3, AR_XmitRate3)].ieeerate; |
| 398 | - tries[3] = MS(ds->ds_ctl2, AR_XmitDataTries3); |
| 399 | - ndx[3] = rate_to_ndx(sn, rate[3]); |
| 400 | + ndx[0] = rate_to_ndx(sn, mrr->rate0); |
| 401 | + ndx[1] = rate_to_ndx(sn, mrr->rate1); |
| 402 | + ndx[2] = rate_to_ndx(sn, mrr->rate2); |
| 403 | + ndx[3] = rate_to_ndx(sn, mrr->rate3); |
| 404 | |
| 405 | #if 0 |
| 406 | DPRINTF(sc, ATH_DEBUG_RATE, "%s: " MAC_FMT " size %u finaltsidx %u tries %u status %u rate/try %u/%u %u/%u %u/%u %u/%u\n", |
| 407 | @@ -636,43 +610,43 @@ ath_rate_tx_complete(struct ath_softc *s |
| 408 | * sample higher rates 1 try at a time doing so |
| 409 | * may unfairly penalize them. |
| 410 | */ |
| 411 | - if (tries[0] && ndx[0] >= 0) { |
| 412 | + if (mrr->retries0 && ndx[0] >= 0) { |
| 413 | update_stats(sc, an, frame_size, |
| 414 | - ndx[0], tries[0], |
| 415 | - ndx[1], tries[1], |
| 416 | - ndx[2], tries[2], |
| 417 | - ndx[3], tries[3], |
| 418 | + ndx[0], mrr->retries0, |
| 419 | + ndx[1], mrr->retries1, |
| 420 | + ndx[2], mrr->retries2, |
| 421 | + ndx[3], mrr->retries3, |
| 422 | short_tries, long_tries, |
| 423 | - long_tries > tries[0]); |
| 424 | - long_tries -= tries[0]; |
| 425 | + long_tries > mrr->retries0); |
| 426 | + long_tries -= mrr->retries0; |
| 427 | |
| 428 | } |
| 429 | |
| 430 | - if (tries[1] && ndx[1] >= 0 && finalTSIdx > 0) { |
| 431 | + if (mrr->retries1 && ndx[1] >= 0 && finalTSIdx > 0) { |
| 432 | update_stats(sc, an, frame_size, |
| 433 | - ndx[1], tries[1], |
| 434 | - ndx[2], tries[2], |
| 435 | - ndx[3], tries[3], |
| 436 | + ndx[1], mrr->retries1, |
| 437 | + ndx[2], mrr->retries2, |
| 438 | + ndx[3], mrr->retries3, |
| 439 | 0, 0, |
| 440 | short_tries, long_tries, |
| 441 | ts->ts_status); |
| 442 | - long_tries -= tries[1]; |
| 443 | + long_tries -= mrr->retries1; |
| 444 | } |
| 445 | |
| 446 | - if (tries[2] && ndx[2] >= 0 && finalTSIdx > 1) { |
| 447 | + if (mrr->retries2 && ndx[2] >= 0 && finalTSIdx > 1) { |
| 448 | update_stats(sc, an, frame_size, |
| 449 | - ndx[2], tries[2], |
| 450 | - ndx[3], tries[3], |
| 451 | + ndx[2], mrr->retries2, |
| 452 | + ndx[3], mrr->retries3, |
| 453 | 0, 0, |
| 454 | 0, 0, |
| 455 | short_tries, long_tries, |
| 456 | ts->ts_status); |
| 457 | - long_tries -= tries[2]; |
| 458 | + long_tries -= mrr->retries2; |
| 459 | } |
| 460 | |
| 461 | - if (tries[3] && ndx[3] >= 0 && finalTSIdx > 2) { |
| 462 | + if (mrr->retries3 && ndx[3] >= 0 && finalTSIdx > 2) { |
| 463 | update_stats(sc, an, frame_size, |
| 464 | - ndx[3], tries[3], |
| 465 | + ndx[3], mrr->retries3, |
| 466 | 0, 0, |
| 467 | 0, 0, |
| 468 | 0, 0, |
| 469 | --- a/ath_rate/sample/sample.h |
| 470 | +++ b/ath_rate/sample/sample.h |
| 471 | @@ -98,35 +98,4 @@ struct sample_node { |
| 472 | }; |
| 473 | #define ATH_NODE_SAMPLE(an) ((struct sample_node *)&an[1]) |
| 474 | |
| 475 | -/* |
| 476 | - * Definitions for pulling the rate and trie counts from |
| 477 | - * a 5212 h/w descriptor. These Don't belong here; the |
| 478 | - * driver should record this information so the rate control |
| 479 | - * code doesn't go groveling around in the descriptor bits. |
| 480 | - */ |
| 481 | -#define ds_ctl2 ds_hw[0] |
| 482 | -#define ds_ctl3 ds_hw[1] |
| 483 | - |
| 484 | -/* TX ds_ctl3 */ |
| 485 | -#define AR_XmitDataTries0 0x000f0000 /* series 0 max attempts */ |
| 486 | -#define AR_XmitDataTries0_S 16 |
| 487 | -#define AR_XmitDataTries1 0x00f00000 /* series 1 max attempts */ |
| 488 | -#define AR_XmitDataTries1_S 20 |
| 489 | -#define AR_XmitDataTries2 0x0f000000 /* series 2 max attempts */ |
| 490 | -#define AR_XmitDataTries2_S 24 |
| 491 | -#define AR_XmitDataTries3 0xf0000000 /* series 3 max attempts */ |
| 492 | -#define AR_XmitDataTries3_S 28 |
| 493 | - |
| 494 | -/* TX ds_ctl3 */ |
| 495 | -#define AR_XmitRate0 0x0000001f /* series 0 tx rate */ |
| 496 | -#define AR_XmitRate0_S 0 |
| 497 | -#define AR_XmitRate1 0x000003e0 /* series 1 tx rate */ |
| 498 | -#define AR_XmitRate1_S 5 |
| 499 | -#define AR_XmitRate2 0x00007c00 /* series 2 tx rate */ |
| 500 | -#define AR_XmitRate2_S 10 |
| 501 | -#define AR_XmitRate3 0x000f8000 /* series 3 tx rate */ |
| 502 | -#define AR_XmitRate3_S 15 |
| 503 | - |
| 504 | -#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) |
| 505 | - |
| 506 | #endif /* _DEV_ATH_RATE_SAMPLE_H */ |
| 507 | |
