| 1 | |
| 2 | #define IFX_CACHE_EXTRA_INVALID_TAG \ |
| 3 | mtc0 zero, CP0_TAGLO, 1; \ |
| 4 | mtc0 zero, CP0_TAGLO, 2; \ |
| 5 | mtc0 zero, CP0_TAGLO, 3; \ |
| 6 | mtc0 zero, CP0_TAGLO, 4; |
| 7 | |
| 8 | #define IFX_CACHE_EXTRA_OPERATION \ |
| 9 | /* set WST bit */ \ |
| 10 | mfc0 a0, CP0_ECC; \ |
| 11 | li a1, ECCF_WST; \ |
| 12 | or a0, a1; \ |
| 13 | mtc0 a0, CP0_ECC; \ |
| 14 | \ |
| 15 | li a0, K0BASE; \ |
| 16 | move a2, t2; /* icacheSize */ \ |
| 17 | move a3, t4; /* icacheLineSize */ \ |
| 18 | move a1, a2; \ |
| 19 | icacheop(a0,a1,a2,a3,(Index_Store_Tag_I)); \ |
| 20 | \ |
| 21 | /* clear WST bit */ \ |
| 22 | mfc0 a0, CP0_ECC; \ |
| 23 | li a1, ~ECCF_WST; \ |
| 24 | and a0, a1; \ |
| 25 | mtc0 a0, CP0_ECC; \ |
| 26 | \ |
| 27 | /* 1: initialise dcache tags. */ \ |
| 28 | \ |
| 29 | /* cache line size */ \ |
| 30 | li a2, CFG_CACHELINE_SIZE; \ |
| 31 | /* kseg0 mem address */ \ |
| 32 | li a1, 0; \ |
| 33 | li a3, CFG_CACHE_SETS * CFG_CACHE_WAYS; \ |
| 34 | 1: \ |
| 35 | /* store tag (invalid, not locked) */ \ |
| 36 | cache 0x8, 0(a1); \ |
| 37 | cache 0x9, 0(a1); \ |
| 38 | \ |
| 39 | add a3, -1; \ |
| 40 | bne a3, zero, 1b; \ |
| 41 | add a1, a2; \ |
| 42 | \ |
| 43 | /* set WST bit */ \ |
| 44 | mfc0 a0, CP0_ECC; \ |
| 45 | li a1, ECCF_WST; \ |
| 46 | or a0, a1; \ |
| 47 | mtc0 a0, CP0_ECC; \ |
| 48 | \ |
| 49 | li a0, K0BASE; \ |
| 50 | move a2, t3; /* dcacheSize */ \ |
| 51 | move a3, t5; /* dcacheLineSize */ \ |
| 52 | move a1, a2; \ |
| 53 | icacheop(a0,a1,a2,a3,(Index_Store_Tag_D)); \ |
| 54 | \ |
| 55 | /* clear WST bit */ \ |
| 56 | mfc0 a0, CP0_ECC; \ |
| 57 | li a1, ~ECCF_WST; \ |
| 58 | and a0, a1; \ |
| 59 | mtc0 a0, CP0_ECC; |
| 60 | |
| 61 | |
