| 1 | /***************************************************************************** |
| 2 | * DANUBE BootROM |
| 3 | * Copyright (c) 2005, Infineon Technologies AG, All rights reserved |
| 4 | * IFAP DC COM SD |
| 5 | *****************************************************************************/ |
| 6 | #ifndef __ASC_H |
| 7 | #define __ASC_H |
| 8 | |
| 9 | #define DANUBEASC_TXFIFO_FL 1 |
| 10 | #define DANUBEASC_RXFIFO_FL 1 |
| 11 | #define DANUBEASC_TXFIFO_FULL 16 |
| 12 | |
| 13 | /* channel operating modes */ |
| 14 | #define ASCOPT_CSIZE 0x00000003 |
| 15 | #define ASCOPT_CS7 0x00000001 |
| 16 | #define ASCOPT_CS8 0x00000002 |
| 17 | #define ASCOPT_PARENB 0x00000004 |
| 18 | #define ASCOPT_STOPB 0x00000008 |
| 19 | #define ASCOPT_PARODD 0x00000010 |
| 20 | #define ASCOPT_CREAD 0x00000020 |
| 21 | |
| 22 | #define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) |
| 23 | |
| 24 | /* ASC input select (0 or 1) */ |
| 25 | #define CONSOLE_TTY 0 |
| 26 | |
| 27 | #define DANUBEASC_TXFIFO_FL 1 |
| 28 | #define DANUBEASC_RXFIFO_FL 1 |
| 29 | #define DANUBEASC_TXFIFO_FULL 16 |
| 30 | |
| 31 | /* interrupt lines masks for the ASC device interrupts*/ |
| 32 | /* change these macroses if it's necessary */ |
| 33 | #define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */ |
| 34 | |
| 35 | #define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */ |
| 36 | #define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */ |
| 37 | #define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */ |
| 38 | #define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */ |
| 39 | #define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */ |
| 40 | #define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */ |
| 41 | #define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */ |
| 42 | |
| 43 | /* interrupt controller access macros */ |
| 44 | #define ASC_INTERRUPTS_ENABLE(X) \ |
| 45 | *((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X; |
| 46 | #define ASC_INTERRUPTS_DISABLE(X) \ |
| 47 | *((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X; |
| 48 | #define ASC_INTERRUPTS_CLEAR(X) \ |
| 49 | *((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X; |
| 50 | |
| 51 | /* CLC register's bits and bitfields */ |
| 52 | #define ASCCLC_DISR 0x00000001 |
| 53 | #define ASCCLC_DISS 0x00000002 |
| 54 | #define ASCCLC_RMCMASK 0x0000FF00 |
| 55 | #define ASCCLC_RMCOFFSET 8 |
| 56 | |
| 57 | /* CON register's bits and bitfields */ |
| 58 | #define ASCCON_MODEMASK 0x0000000f |
| 59 | #define ASCCON_M_8ASYNC 0x0 |
| 60 | #define ASCCON_M_8IRDA 0x1 |
| 61 | #define ASCCON_M_7ASYNC 0x2 |
| 62 | #define ASCCON_M_7IRDA 0x3 |
| 63 | #define ASCCON_WLSMASK 0x0000000c |
| 64 | #define ASCCON_WLSOFFSET 2 |
| 65 | #define ASCCON_WLS_8BIT 0x0 |
| 66 | #define ASCCON_WLS_7BIT 0x1 |
| 67 | #define ASCCON_PEN 0x00000010 |
| 68 | #define ASCCON_ODD 0x00000020 |
| 69 | #define ASCCON_SP 0x00000040 |
| 70 | #define ASCCON_STP 0x00000080 |
| 71 | #define ASCCON_BRS 0x00000100 |
| 72 | #define ASCCON_FDE 0x00000200 |
| 73 | #define ASCCON_ERRCLK 0x00000400 |
| 74 | #define ASCCON_EMMASK 0x00001800 |
| 75 | #define ASCCON_EMOFFSET 11 |
| 76 | #define ASCCON_EM_ECHO_OFF 0x0 |
| 77 | #define ASCCON_EM_ECHO_AB 0x1 |
| 78 | #define ASCCON_EM_ECHO_ON 0x2 |
| 79 | #define ASCCON_LB 0x00002000 |
| 80 | #define ASCCON_ACO 0x00004000 |
| 81 | #define ASCCON_R 0x00008000 |
| 82 | #define ASCCON_PAL 0x00010000 |
| 83 | #define ASCCON_FEN 0x00020000 |
| 84 | #define ASCCON_RUEN 0x00040000 |
| 85 | #define ASCCON_ROEN 0x00080000 |
| 86 | #define ASCCON_TOEN 0x00100000 |
| 87 | #define ASCCON_BEN 0x00200000 |
| 88 | #define ASCCON_TXINV 0x01000000 |
| 89 | #define ASCCON_RXINV 0x02000000 |
| 90 | #define ASCCON_TXMSB 0x04000000 |
| 91 | #define ASCCON_RXMSB 0x08000000 |
| 92 | |
| 93 | /* STATE register's bits and bitfields */ |
| 94 | #define ASCSTATE_REN 0x00000001 |
| 95 | #define ASCSTATE_PE 0x00010000 |
| 96 | #define ASCSTATE_FE 0x00020000 |
| 97 | #define ASCSTATE_RUE 0x00040000 |
| 98 | #define ASCSTATE_ROE 0x00080000 |
| 99 | #define ASCSTATE_TOE 0x00100000 |
| 100 | #define ASCSTATE_BE 0x00200000 |
| 101 | #define ASCSTATE_TXBVMASK 0x07000000 |
| 102 | #define ASCSTATE_TXBVOFFSET 24 |
| 103 | #define ASCSTATE_TXEOM 0x08000000 |
| 104 | #define ASCSTATE_RXBVMASK 0x70000000 |
| 105 | #define ASCSTATE_RXBVOFFSET 28 |
| 106 | #define ASCSTATE_RXEOM 0x80000000 |
| 107 | |
| 108 | /* WHBSTATE register's bits and bitfields */ |
| 109 | #define ASCWHBSTATE_CLRREN 0x00000001 |
| 110 | #define ASCWHBSTATE_SETREN 0x00000002 |
| 111 | #define ASCWHBSTATE_CLRPE 0x00000004 |
| 112 | #define ASCWHBSTATE_CLRFE 0x00000008 |
| 113 | #define ASCWHBSTATE_CLRRUE 0x00000010 |
| 114 | #define ASCWHBSTATE_CLRROE 0x00000020 |
| 115 | #define ASCWHBSTATE_CLRTOE 0x00000040 |
| 116 | #define ASCWHBSTATE_CLRBE 0x00000080 |
| 117 | #define ASCWHBSTATE_SETPE 0x00000100 |
| 118 | #define ASCWHBSTATE_SETFE 0x00000200 |
| 119 | #define ASCWHBSTATE_SETRUE 0x00000400 |
| 120 | #define ASCWHBSTATE_SETROE 0x00000800 |
| 121 | #define ASCWHBSTATE_SETTOE 0x00001000 |
| 122 | #define ASCWHBSTATE_SETBE 0x00002000 |
| 123 | |
| 124 | /* ABCON register's bits and bitfields */ |
| 125 | #define ASCABCON_ABEN 0x0001 |
| 126 | #define ASCABCON_AUREN 0x0002 |
| 127 | #define ASCABCON_ABSTEN 0x0004 |
| 128 | #define ASCABCON_ABDETEN 0x0008 |
| 129 | #define ASCABCON_FCDETEN 0x0010 |
| 130 | |
| 131 | /* FDV register mask, offset and bitfields*/ |
| 132 | #define ASCFDV_VALUE_MASK 0x000001FF |
| 133 | |
| 134 | /* WHBABCON register's bits and bitfields */ |
| 135 | #define ASCWHBABCON_CLRABEN 0x0001 |
| 136 | #define ASCWHBABCON_SETABEN 0x0002 |
| 137 | |
| 138 | /* ABSTAT register's bits and bitfields */ |
| 139 | #define ASCABSTAT_FCSDET 0x0001 |
| 140 | #define ASCABSTAT_FCCDET 0x0002 |
| 141 | #define ASCABSTAT_SCSDET 0x0004 |
| 142 | #define ASCABSTAT_SCCDET 0x0008 |
| 143 | #define ASCABSTAT_DETWAIT 0x0010 |
| 144 | |
| 145 | /* WHBABSTAT register's bits and bitfields */ |
| 146 | #define ASCWHBABSTAT_CLRFCSDET 0x0001 |
| 147 | #define ASCWHBABSTAT_SETFCSDET 0x0002 |
| 148 | #define ASCWHBABSTAT_CLRFCCDET 0x0004 |
| 149 | #define ASCWHBABSTAT_SETFCCDET 0x0008 |
| 150 | #define ASCWHBABSTAT_CLRSCSDET 0x0010 |
| 151 | #define ASCWHBABSTAT_SETSCSDET 0x0020 |
| 152 | #define ASCWHBABSTAT_CLRSCCDET 0x0040 |
| 153 | #define ASCWHBABSTAT_SETSCCDET 0x0080 |
| 154 | #define ASCWHBABSTAT_CLRDETWAIT 0x0100 |
| 155 | #define ASCWHBABSTAT_SETDETWAIT 0x0200 |
| 156 | |
| 157 | /* TXFCON register's bits and bitfields */ |
| 158 | #define ASCTXFCON_TXFIFO1 0x00000400 |
| 159 | #define ASCTXFCON_TXFEN 0x0001 |
| 160 | #define ASCTXFCON_TXFFLU 0x0002 |
| 161 | #define ASCTXFCON_TXFITLMASK 0x3F00 |
| 162 | #define ASCTXFCON_TXFITLOFF 8 |
| 163 | |
| 164 | /* RXFCON register's bits and bitfields */ |
| 165 | #define ASCRXFCON_RXFIFO1 0x00000400 |
| 166 | #define ASCRXFCON_RXFEN 0x0001 |
| 167 | #define ASCRXFCON_RXFFLU 0x0002 |
| 168 | #define ASCRXFCON_RXFITLMASK 0x3F00 |
| 169 | #define ASCRXFCON_RXFITLOFF 8 |
| 170 | |
| 171 | /* FSTAT register's bits and bitfields */ |
| 172 | #define ASCFSTAT_RXFFLMASK 0x003F |
| 173 | #define ASCFSTAT_TXFFLMASK 0x3F00 |
| 174 | #define ASCFSTAT_TXFFLOFF 8 |
| 175 | |
| 176 | typedef struct /* DanubeAsc_t */ |
| 177 | { |
| 178 | volatile unsigned long asc_clc; /*0x0000*/ |
| 179 | volatile unsigned long asc_pisel; /*0x0004*/ |
| 180 | volatile unsigned long asc_id; /*0x0008*/ |
| 181 | volatile unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/ |
| 182 | volatile unsigned long asc_con; /*0x0010*/ |
| 183 | volatile unsigned long asc_state; /*0x0014*/ |
| 184 | volatile unsigned long asc_whbstate; /*0x0018*/ |
| 185 | volatile unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/ |
| 186 | volatile unsigned long asc_tbuf; /*0x0020*/ |
| 187 | volatile unsigned long asc_rbuf; /*0x0024*/ |
| 188 | volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/ |
| 189 | volatile unsigned long asc_abcon; /*0x0030*/ |
| 190 | volatile unsigned long asc_abstat; /* not used */ /*0x0034*/ |
| 191 | volatile unsigned long asc_whbabcon; /*0x0038*/ |
| 192 | volatile unsigned long asc_whbabstat; /* not used */ /*0x003C*/ |
| 193 | volatile unsigned long asc_rxfcon; /*0x0040*/ |
| 194 | volatile unsigned long asc_txfcon; /*0x0044*/ |
| 195 | volatile unsigned long asc_fstat; /*0x0048*/ |
| 196 | volatile unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/ |
| 197 | volatile unsigned long asc_bg; /*0x0050*/ |
| 198 | volatile unsigned long asc_bg_timer; /*0x0054*/ |
| 199 | volatile unsigned long asc_fdv; /*0x0058*/ |
| 200 | volatile unsigned long asc_pmw; /*0x005C*/ |
| 201 | volatile unsigned long asc_modcon; /*0x0060*/ |
| 202 | volatile unsigned long asc_modstat; /*0x0064*/ |
| 203 | volatile unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/ |
| 204 | volatile unsigned long asc_sfcc; /*0x0070*/ |
| 205 | volatile unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/ |
| 206 | volatile unsigned long asc_eomcon; /*0x0080*/ |
| 207 | volatile unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/ |
| 208 | volatile unsigned long asc_dmacon; /*0x00EC*/ |
| 209 | volatile unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/ |
| 210 | volatile unsigned long asc_irnen; /*0x00F4*/ |
| 211 | volatile unsigned long asc_irnicr; /*0x00F8*/ |
| 212 | volatile unsigned long asc_irncr; /*0x00FC*/ |
| 213 | } DanubeAsc_t; |
| 214 | |
| 215 | int asc_init (void); |
| 216 | void asc_puts (const char *s); |
| 217 | void asc_putc (const char c); |
| 218 | int asc_getc (void); |
| 219 | |
| 220 | #endif /* __ASC_H */ |
| 221 | |
