| 1 | /************************************************************************ |
| 2 | * |
| 3 | * Copyright (c) 2005 |
| 4 | * Infineon Technologies AG |
| 5 | * St. Martin Strasse 53; 81669 Muenchen; Germany |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * as published by the Free Software Foundation; either version |
| 10 | * 2 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | ************************************************************************/ |
| 13 | |
| 14 | /***********************************************************************/ |
| 15 | /* Module : DMA register address and bits */ |
| 16 | /***********************************************************************/ |
| 17 | |
| 18 | #define INCA_IP2_DMA (KSEG1+0x14101000) |
| 19 | /***********************************************************************/ |
| 20 | #define CONFIGURATION_REGISTERS_CLC (INCA_IP2_DMA + 0x00) |
| 21 | #define CONFIGURATION_REGISTERS_ID (INCA_IP2_DMA + 0x08) |
| 22 | #define GENERAL_REGISTERS_DMA_CTRL (INCA_IP2_DMA + 0x10) |
| 23 | #define CHANNEL_RELATED_REGISTERS_DMA_CS (INCA_IP2_DMA + 0x18) |
| 24 | #define CHANNEL_RELATED_REGISTERS_DMA_CCTRL (INCA_IP2_DMA + 0x1C) |
| 25 | #define CHANNEL_RELATED_REGISTERS_DMA_CDBA (INCA_IP2_DMA + 0x20) |
| 26 | #define CHANNEL_RELATED_REGISTERS_DMA_CDLEN (INCA_IP2_DMA + 0x24) |
| 27 | #define CHANNEL_RELATED_REGISTERS_DMA_CIE (INCA_IP2_DMA + 0x2C) |
| 28 | #define CHANNEL_RELATED_REGISTERS_DMA_CIS (INCA_IP2_DMA + 0x28) |
| 29 | #define CHANNEL_RELATED_REGISTERS_DMA_CPOLL (INCA_IP2_DMA + 0x14) |
| 30 | |
| 31 | #define PORT_RELATED_REGISTERS_DMA_PS (INCA_IP2_DMA + 0x40) |
| 32 | #define PORT_RELATED_REGISTERS_DMA_PCTRL (INCA_IP2_DMA + 0x44) |
| 33 | |
| 34 | #define INTERRUPT_NODE_REGISTERS_DMA_IRNEN (INCA_IP2_DMA + 0xF4) |
| 35 | #define INTERRUPT_NODE_REGISTERS_DMA_IRNCR (INCA_IP2_DMA + 0xF8) |
| 36 | #define INTERRUPT_NODE_REGISTERS_DMA_IRNICR (INCA_IP2_DMA + 0xFC) |
| 37 | |
| 38 | #if 0 |
| 39 | /* ISR */ |
| 40 | #define DMA_ISR_RDERR 0x20 |
| 41 | #define DMA_ISR_CMDCPT 0x10 |
| 42 | #define DMA_ISR_CPT 0x8 |
| 43 | #define DMA_ISR_DURR 0x4 |
| 44 | #define DMA_ISR_EOP 0x2 |
| 45 | #endif |
| 46 | #define DMA_RESET_CHANNEL 0x00000002 |
| 47 | #define DMA_ENABLE_CHANNEL 0x00000001 |
| 48 | #define DMA_DESC_BYTEOFF_SHIFT 22 |
| 49 | |
| 50 | #define DMA_POLLING_ENABLE 0x80000000 |
| 51 | #define DMA_POLLING_CNT 0x50 /*minimum 0x10, max 0xfff0*/ |
| 52 | |
| 53 | /***********************************************************************/ |
| 54 | /* Module : ICU register address and bits */ |
| 55 | /***********************************************************************/ |
| 56 | |
| 57 | #define INCA_IP2_ICU (KSEG1+0x1F880200) |
| 58 | /***********************************************************************/ |
| 59 | |
| 60 | #define INCA_IP2_ICU_IM0_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0000)) |
| 61 | #define INCA_IP2_ICU_IM0_IER ((volatile u32*)(INCA_IP2_ICU + 0x0008)) |
| 62 | #define INCA_IP2_ICU_IM0_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0010)) |
| 63 | #define INCA_IP2_ICU_IM0_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0018)) |
| 64 | #define INCA_IP2_ICU_IM0_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0020)) |
| 65 | #define INCA_IP2_ICU_IM0_IMR_IID (1 << 31) |
| 66 | #define INCA_IP2_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) |
| 67 | #define INCA_IP2_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) |
| 68 | #define INCA_IP2_ICU_IM0_IR(value) (1 << (value)) |
| 69 | |
| 70 | #define INCA_IP2_ICU_IM1_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0028)) |
| 71 | #define INCA_IP2_ICU_IM1_IER ((volatile u32*)(INCA_IP2_ICU + 0x0030)) |
| 72 | #define INCA_IP2_ICU_IM1_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0038)) |
| 73 | #define INCA_IP2_ICU_IM1_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0040)) |
| 74 | #define INCA_IP2_ICU_IM1_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0048)) |
| 75 | #define INCA_IP2_ICU_IM1_IMR_IID (1 << 31) |
| 76 | #define INCA_IP2_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) |
| 77 | #define INCA_IP2_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) |
| 78 | #define INCA_IP2_ICU_IM1_IR(value) (1 << (value)) |
| 79 | |
| 80 | #define INCA_IP2_ICU_IM2_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0050)) |
| 81 | #define INCA_IP2_ICU_IM2_IER ((volatile u32*)(INCA_IP2_ICU + 0x0058)) |
| 82 | #define INCA_IP2_ICU_IM2_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0060)) |
| 83 | #define INCA_IP2_ICU_IM2_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0068)) |
| 84 | #define INCA_IP2_ICU_IM2_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0070)) |
| 85 | #define INCA_IP2_ICU_IM2_IMR_IID (1 << 31) |
| 86 | #define INCA_IP2_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) |
| 87 | #define INCA_IP2_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) |
| 88 | #define INCA_IP2_ICU_IM2_IR(value) (1 << (value)) |
| 89 | |
| 90 | #define INCA_IP2_ICU_IM3_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0078)) |
| 91 | #define INCA_IP2_ICU_IM3_IER ((volatile u32*)(INCA_IP2_ICU + 0x0080)) |
| 92 | #define INCA_IP2_ICU_IM3_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0088)) |
| 93 | #define INCA_IP2_ICU_IM3_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0090)) |
| 94 | #define INCA_IP2_ICU_IM3_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0098)) |
| 95 | #define INCA_IP2_ICU_IM3_IMR_IID (1 << 31) |
| 96 | #define INCA_IP2_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) |
| 97 | #define INCA_IP2_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) |
| 98 | #define INCA_IP2_ICU_IM3_IR(value) (1 << (value)) |
| 99 | |
| 100 | #define INCA_IP2_ICU_IM4_ISR ((volatile u32*)(INCA_IP2_ICU + 0x00A0)) |
| 101 | #define INCA_IP2_ICU_IM4_IER ((volatile u32*)(INCA_IP2_ICU + 0x00A8)) |
| 102 | #define INCA_IP2_ICU_IM4_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x00B0)) |
| 103 | #define INCA_IP2_ICU_IM4_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x00B8)) |
| 104 | #define INCA_IP2_ICU_IM4_IMR ((volatile u32*)(INCA_IP2_ICU + 0x00C0)) |
| 105 | #define INCA_IP2_ICU_IM4_IMR_IID (1 << 31) |
| 106 | #define INCA_IP2_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) |
| 107 | #define INCA_IP2_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) |
| 108 | #define INCA_IP2_ICU_IM4_IR(value) (1 << (value)) |
| 109 | |
| 110 | #define INCA_IP2_ICU_IM5_ISR ((volatile u32*)(INCA_IP2_ICU + 0x00C8)) |
| 111 | #define INCA_IP2_ICU_IM5_IER ((volatile u32*)(INCA_IP2_ICU + 0x00D0)) |
| 112 | #define INCA_IP2_ICU_IM5_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x00D8)) |
| 113 | #define INCA_IP2_ICU_IM5_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x00E0)) |
| 114 | #define INCA_IP2_ICU_IM5_IMR ((volatile u32*)(INCA_IP2_ICU + 0x00E8)) |
| 115 | #define INCA_IP2_ICU_IM5_IMR_IID (1 << 31) |
| 116 | #define INCA_IP2_ICU_IM5_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) |
| 117 | #define INCA_IP2_ICU_IM5_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) |
| 118 | #define INCA_IP2_ICU_IM5_IR(value) (1 << (value)) |
| 119 | |
| 120 | |
| 121 | /***********************************************************************/ |
| 122 | /* Module : CGU register address and bits */ |
| 123 | /***********************************************************************/ |
| 124 | |
| 125 | #define INCA_IP2_CGU (KSEG1+0x1F100800) |
| 126 | /***********************************************************************/ |
| 127 | |
| 128 | #define INCA_IP2_CGU_PLL2CR ((volatile u32*)(INCA_IP2_CGU + 0x0008)) |
| 129 | #define INCA_IP2_CGU_FBSCR ((volatile u32*)(INCA_IP2_CGU + 0x0018)) |
| 130 | #define INCA_IP2_CGU_FBSCR_LPBSDIV_GET(value) (((value) >> 6) & ((1 << 2) - 1)) |
| 131 | #define INCA_IP2_CGU_FBSCR_DIV0_GET(value) (((value) >> 0) & ((1 << 3) - 1)) |
| 132 | #define INCA_IP2_CGU_FBSCR_DIV1_GET(value) (((value) >> 4) & ((1 << 2) - 1)) |
| 133 | |
| 134 | /***********************************************************************/ |
| 135 | /* Module : MPS register address and bits */ |
| 136 | /***********************************************************************/ |
| 137 | |
| 138 | #define INCA_IP2_MPS (KSEG1+0x1F101400) |
| 139 | /***********************************************************************/ |
| 140 | |
| 141 | #define INCA_IP2_MPS_CHIPID ((volatile u32*)(INCA_IP2_MPS + 0x0344)) |
| 142 | #define INCA_IP2_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) |
| 143 | #define INCA_IP2_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) |
| 144 | #define INCA_IP2_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) |
| 145 | #define INCA_IP2_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) |
| 146 | #define INCA_IP2_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) |
| 147 | #define INCA_IP2_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) |
| 148 | |
| 149 | |
| 150 | /* voice channel 0 ... 3 interrupt enable register */ |
| 151 | #define INCA_IP2_MPS_VC0ENR ((volatile u32*)(INCA_IP2_MPS + 0x0000)) |
| 152 | #define INCA_IP2_MPS_VC1ENR ((volatile u32*)(INCA_IP2_MPS + 0x0004)) |
| 153 | #define INCA_IP2_MPS_VC2ENR ((volatile u32*)(INCA_IP2_MPS + 0x0008)) |
| 154 | #define INCA_IP2_MPS_VC3ENR ((volatile u32*)(INCA_IP2_MPS + 0x000C)) |
| 155 | /* voice channel 0 ... 3 interrupt status read register */ |
| 156 | #define INCA_IP2_MPS_RVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0010)) |
| 157 | #define INCA_IP2_MPS_RVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0014)) |
| 158 | #define INCA_IP2_MPS_RVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0018)) |
| 159 | #define INCA_IP2_MPS_RVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x001C)) |
| 160 | /* voice channel 0 ... 3 interrupt status set register */ |
| 161 | #define INCA_IP2_MPS_SVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0020)) |
| 162 | #define INCA_IP2_MPS_SVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0024)) |
| 163 | #define INCA_IP2_MPS_SVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0028)) |
| 164 | #define INCA_IP2_MPS_SVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x002C)) |
| 165 | /* voice channel 0 ... 3 interrupt status clear register */ |
| 166 | #define INCA_IP2_MPS_CVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0030)) |
| 167 | #define INCA_IP2_MPS_CVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0034)) |
| 168 | #define INCA_IP2_MPS_CVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0038)) |
| 169 | #define INCA_IP2_MPS_CVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x003C)) |
| 170 | /* common status 0 and 1 read register */ |
| 171 | #define INCA_IP2_MPS_RAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0040)) |
| 172 | #define INCA_IP2_MPS_RAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x0044)) |
| 173 | /* common status 0 and 1 set register */ |
| 174 | #define INCA_IP2_MPS_SAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0048)) |
| 175 | #define INCA_IP2_MPS_SAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x004C)) |
| 176 | /* common status 0 and 1 clear register */ |
| 177 | #define INCA_IP2_MPS_CAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0050)) |
| 178 | #define INCA_IP2_MPS_CAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x0054)) |
| 179 | /* notification enable register */ |
| 180 | #define INCA_IP2_MPS_CPU0_NFER ((volatile u32*)(INCA_IP2_MPS + 0x0060)) |
| 181 | #define INCA_IP2_MPS_CPU1_NFER ((volatile u32*)(INCA_IP2_MPS + 0x0064)) |
| 182 | /* CPU to CPU interrup request register */ |
| 183 | #define INCA_IP2_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(INCA_IP2_MPS + 0x0070)) |
| 184 | #define INCA_IP2_MPS_CPU0_2_CPU1_IER ((volatile u32*)(INCA_IP2_MPS + 0x0074)) |
| 185 | /* Global interrupt request and request enable register */ |
| 186 | #define INCA_IP2_MPS_GIRR ((volatile u32*)(INCA_IP2_MPS + 0x0078)) |
| 187 | #define INCA_IP2_MPS_GIER ((volatile u32*)(INCA_IP2_MPS + 0x007C)) |
| 188 | |
| 189 | /* Addresses of enable registers not yet defined |
| 190 | #define INCA_IP2_MPS_AD0ENR ((volatile u32*)(INCA_IP2_MPS + 0x????)) |
| 191 | #define INCA_IP2_MPS_AD1ENR ((volatile u32*)(INCA_IP2_MPS + 0x????)) |
| 192 | */ |
| 193 | |
| 194 | |
| 195 | /***********************************************************************/ |
| 196 | /* Module : ASC0 register address and bits */ |
| 197 | /***********************************************************************/ |
| 198 | |
| 199 | #define INCA_IP2_ASC0 (KSEG1+0x1E000400) |
| 200 | /***********************************************************************/ |
| 201 | |
| 202 | #define INCA_IP2_ASC0_TBUF ((volatile u32*)(INCA_IP2_ASC0 + 0x0020)) |
| 203 | #define INCA_IP2_ASC0_RBUF ((volatile u32*)(INCA_IP2_ASC0 + 0x0024)) |
| 204 | #define INCA_IP2_ASC0_FSTAT ((volatile u32*)(INCA_IP2_ASC0 + 0x0048)) |
| 205 | #define INCA_IP2_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) |
| 206 | #define INCA_IP2_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) |
| 207 | #define INCA_IP2_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) |
| 208 | #define INCA_IP2_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) |
| 209 | #define INCA_IP2_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) |
| 210 | #define INCA_IP2_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) |
| 211 | #define INCA_IP2_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) |
| 212 | #define INCA_IP2_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) |
| 213 | |
| 214 | |
| 215 | /***********************************************************************/ |
| 216 | /* Module : ASC1 register address and bits */ |
| 217 | /***********************************************************************/ |
| 218 | |
| 219 | #define INCA_IP2_ASC1 (KSEG1+0x1E000800) |
| 220 | /***********************************************************************/ |
| 221 | |
| 222 | #define INCA_IP2_ASC1_TBUF ((volatile u32*)(INCA_IP2_ASC1 + 0x0020)) |
| 223 | #define INCA_IP2_ASC1_RBUF ((volatile u32*)(INCA_IP2_ASC1 + 0x0024)) |
| 224 | #define INCA_IP2_ASC1_FSTAT ((volatile u32*)(INCA_IP2_ASC1 + 0x0048)) |
| 225 | #define INCA_IP2_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) |
| 226 | #define INCA_IP2_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) |
| 227 | #define INCA_IP2_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) |
| 228 | #define INCA_IP2_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) |
| 229 | #define INCA_IP2_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) |
| 230 | #define INCA_IP2_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) |
| 231 | #define INCA_IP2_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) |
| 232 | #define INCA_IP2_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) |
| 233 | |
| 234 | |
| 235 | /***********************************************************************/ |
| 236 | /* Module : RCU register address and bits */ |
| 237 | /***********************************************************************/ |
| 238 | |
| 239 | #define INCA_IP2_RCU (KSEG1+0x1E001C00) |
| 240 | /***********************************************************************/ |
| 241 | |
| 242 | /***Reset Request Register***/ |
| 243 | #define INCA_IP2_RCU_RST_REQ ((volatile u32*)(INCA_IP2_RCU + 0x0000)) |
| 244 | #define INCA_IP2_RCU_RST_REQ_CPU0 (1 << 31) |
| 245 | #define INCA_IP2_RCU_RST_REQ_CPU1 (1 << 30) |
| 246 | #define INCA_IP2_RCU_RST_REQ_CPUSUB (1 << 29) |
| 247 | #define INCA_IP2_RCU_RST_REQ_HRST (1 << 28) |
| 248 | #define INCA_IP2_RCU_RST_REQ_WDT0 (1 << 27) |
| 249 | #define INCA_IP2_RCU_RST_REQ_WDT1 (1 << 26) |
| 250 | #define INCA_IP2_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1)) |
| 251 | #define INCA_IP2_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23) |
| 252 | #define INCA_IP2_RCU_RST_REQ_SWTBOOT (1 << 22) |
| 253 | #define INCA_IP2_RCU_RST_REQ_DMA (1 << 21) |
| 254 | #define INCA_IP2_RCU_RST_REQ_ETHPHY1 (1 << 20) |
| 255 | #define INCA_IP2_RCU_RST_REQ_ETHPHY0 (1 << 19) |
| 256 | #define INCA_IP2_RCU_RST_REQ_CPU0_BR (1 << 18) |
| 257 | |
| 258 | /* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ |
| 259 | #define INCA_IP2_RCU_RST_REQ_ALL 0xFC380000 |
| 260 | |
| 261 | /***NMI Status Register***/ |
| 262 | #define INCA_IP2_RCU_NMISR ((volatile u32*)(INCA_IP2_RCU + 0x00F4)) |
| 263 | #define INCA_IP2_RCU_NMISR_NMIEXT (1 << 2) |
| 264 | #define INCA_IP2_RCU_NMISR_NMIPLL2 (1 << 1) |
| 265 | #define INCA_IP2_RCU_NMISR_NMIPLL1 (1 << 0) |
| 266 | |
| 267 | |
| 268 | /***********************************************************************/ |
| 269 | /* Module : WDT register address and bits */ |
| 270 | /***********************************************************************/ |
| 271 | |
| 272 | #define INCA_IP2_WDT (KSEG1+0x1F880000) |
| 273 | /***********************************************************************/ |
| 274 | |
| 275 | /***Watchdog Timer Control Register ***/ |
| 276 | #define INCA_IP2_WDT_BIU_WDT_CR ((volatile u32*)(INCA_IP2_WDT + 0x03F0)) |
| 277 | #define INCA_IP2_WDT_BIU_WDT_CR_GEN (1 << 31) |
| 278 | #define INCA_IP2_WDT_BIU_WDT_CR_DSEN (1 << 30) |
| 279 | #define INCA_IP2_WDT_BIU_WDT_CR_LPEN (1 << 29) |
| 280 | #define INCA_IP2_WDT_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) |
| 281 | #define INCA_IP2_WDT_BIU_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) |
| 282 | #define INCA_IP2_WDT_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) |
| 283 | #define INCA_IP2_WDT_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) |
| 284 | #define INCA_IP2_WDT_BIU_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) |
| 285 | #define INCA_IP2_WDT_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) |
| 286 | #define INCA_IP2_WDT_BIU_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) |
| 287 | #define INCA_IP2_WDT_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) |
| 288 | |
| 289 | /***Watchdog Timer Status Register***/ |
| 290 | #define INCA_IP2_WDT_BIU_WDT_SR ((volatile u32*)(INCA_IP2_WDT + 0x03F8)) |
| 291 | #define INCA_IP2_WDT_BIU_WDT_SR_EN (1 << 31) |
| 292 | #define INCA_IP2_WDT_BIU_WDT_SR_AE (1 << 30) |
| 293 | #define INCA_IP2_WDT_BIU_WDT_SR_PRW (1 << 29) |
| 294 | #define INCA_IP2_WDT_BIU_WDT_SR_EXP (1 << 28) |
| 295 | #define INCA_IP2_WDT_BIU_WDT_SR_PWD (1 << 27) |
| 296 | #define INCA_IP2_WDT_BIU_WDT_SR_DS (1 << 26) |
| 297 | #define INCA_IP2_WDT_BIU_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) |
| 298 | #define INCA_IP2_WDT_BIU_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) |
| 299 | |
| 300 | |
| 301 | /***********************************************************************/ |
| 302 | /* Module : BCU0 register address and bits */ |
| 303 | /***********************************************************************/ |
| 304 | |
| 305 | #define INCA_IP2_BCU0 (KSEG1+0x14100000) |
| 306 | /***********************************************************************/ |
| 307 | |
| 308 | #define INCA_IP2_BCU0_CON ((volatile u32*)(INCA_IP2_BCU0 + 0x0010)) |
| 309 | #define INCA_IP2_BCU0_ECON ((volatile u32*)(INCA_IP2_BCU0 + 0x0020)) |
| 310 | #define INCA_IP2_BCU0_EADD ((volatile u32*)(INCA_IP2_BCU0 + 0x0024)) |
| 311 | #define INCA_IP2_BCU0_EDAT ((volatile u32*)(INCA_IP2_BCU0 + 0x0028)) |
| 312 | #define INCA_IP2_BCU0_IRNCR1 ((volatile u32*)(INCA_IP2_BCU0 + 0x00F8)) |
| 313 | #define INCA_IP2_BCU0_IRNCR0 ((volatile u32*)(INCA_IP2_BCU0 + 0x00FC)) |
| 314 | |
| 315 | |
| 316 | /***********************************************************************/ |
| 317 | /* Module : BCU1 register address and bits */ |
| 318 | /***********************************************************************/ |
| 319 | |
| 320 | #define INCA_IP2_BCU1 (KSEG1+0x1E000000) |
| 321 | /***********************************************************************/ |
| 322 | |
| 323 | #define INCA_IP2_BCU1_CON ((volatile u32*)(INCA_IP2_BCU1 + 0x0010)) |
| 324 | #define INCA_IP2_BCU1_ECON ((volatile u32*)(INCA_IP2_BCU1 + 0x0020)) |
| 325 | #define INCA_IP2_BCU1_EADD ((volatile u32*)(INCA_IP2_BCU1 + 0x0024)) |
| 326 | #define INCA_IP2_BCU1_EDAT ((volatile u32*)(INCA_IP2_BCU1 + 0x0028)) |
| 327 | #define INCA_IP2_BCU1_IRNCR1 ((volatile u32*)(INCA_IP2_BCU1 + 0x00F8)) |
| 328 | #define INCA_IP2_BCU1_IRNCR0 ((volatile u32*)(INCA_IP2_BCU1 + 0x00FC)) |
| 329 | |
| 330 | |
| 331 | /***********************************************************************/ |
| 332 | /* Module : MC register address and bits */ |
| 333 | /***********************************************************************/ |
| 334 | |
| 335 | #define INCA_IP2_MC (KSEG1+0x1F800000) |
| 336 | /***********************************************************************/ |
| 337 | |
| 338 | #define INCA_IP2_MC_ERRCAUSE ((volatile u32*)(INCA_IP2_MC + 0x0010)) |
| 339 | #define INCA_IP2_MC_ERRADDR ((volatile u32*)(INCA_IP2_MC + 0x0020)) |
| 340 | #define INCA_IP2_MC_CON ((volatile u32*)(INCA_IP2_MC + 0x0060)) |
| 341 | |
| 342 | /***********************************************************************/ |
| 343 | /* Module : MC SDRAM register address and bits */ |
| 344 | /***********************************************************************/ |
| 345 | #define INCA_IP2_SDRAM (KSEG1+0x1F800200) |
| 346 | /***********************************************************************/ |
| 347 | #define INCA_IP2_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP2_SDRAM + 0x0040)) |
| 348 | |
| 349 | /***********************************************************************/ |
| 350 | /* Module : MC DDR register address and bits */ |
| 351 | /***********************************************************************/ |
| 352 | #define INCA_IP2_DDR (KSEG1+0x1F801000) |
| 353 | /***********************************************************************/ |
| 354 | #define INCA_IP2_DDR_MC_DC19 ((volatile u32*)(INCA_IP2_DDR + 0x0130)) |
| 355 | #define INCA_IP2_DDR_MC_DC20 ((volatile u32*)(INCA_IP2_DDR + 0x0140)) |
| 356 | |
| 357 | |
| 358 | /***********************************************************************/ |
| 359 | /* Module : PMS register address and bits */ |
| 360 | /***********************************************************************/ |
| 361 | |
| 362 | #define INCA_IP2_PMS (KSEG1 + 0x1F100C00) |
| 363 | |
| 364 | #define INCA_IP2_PMS_PMS_SR ((volatile u32*) (INCA_IP2_PMS + 0x0000)) |
| 365 | #define INCA_IP2_PMS_PMS_SR_ASC1 (1 << 14) |
| 366 | #define INCA_IP2_PMS_PMS_SR_ASC0 (1 << 13) |
| 367 | #define INCA_IP2_PMS_PMS_GEN ((volatile u32*) (INCA_IP2_PMS + 0x0004)) |
| 368 | #define INCA_IP2_PMS_PMS_GEN_DMA (1 << 16) |
| 369 | #define INCA_IP2_PMS_PMS_GEN_ASC1 (1 << 14) |
| 370 | #define INCA_IP2_PMS_PMS_GEN_ASC0 (1 << 13) |
| 371 | #define INCA_IP2_PMS_PMS_GEN_SPI0 (1 << 11) |
| 372 | #define INCA_IP2_PMS_PMS_GEN_SPI1 (1 << 12) |
| 373 | #define INCA_IP2_PMS_PMS_CFG ((volatile u32*) (INCA_IP2_PMS + 0x0008)) |
| 374 | |
| 375 | |
| 376 | /***********************************************************************/ |
| 377 | /* Module : GPIO register address and bits */ |
| 378 | /***********************************************************************/ |
| 379 | |
| 380 | #define INCA_IP2_GPIO (KSEG1 + 0x1F102600) |
| 381 | |
| 382 | #define INCA_IP2_GPIO_OUT ((volatile u32*) (INCA_IP2_GPIO + 0x0000)) |
| 383 | #define INCA_IP2_GPIO_IN ((volatile u32*) (INCA_IP2_GPIO + 0x0004)) |
| 384 | #define INCA_IP2_GPIO_DIR ((volatile u32*) (INCA_IP2_GPIO + 0x0008)) |
| 385 | #define INCA_IP2_GPIO_ALTSEL1 ((volatile u32*) (INCA_IP2_GPIO + 0x000C)) |
| 386 | #define INCA_IP2_GPIO_ALTSEL2 ((volatile u32*) (INCA_IP2_GPIO + 0x0010)) |
| 387 | #define INCA_IP2_GPIO_STOFF ((volatile u32*) (INCA_IP2_GPIO + 0x0014)) |
| 388 | #define INCA_IP2_GPIO_OD ((volatile u32*) (INCA_IP2_GPIO + 0x0018)) |
| 389 | #define INCA_IP2_GPIO_PUDEB ((volatile u32*) (INCA_IP2_GPIO + 0x001C)) |
| 390 | |
| 391 | /***********************************************************************/ |
| 392 | /* Module : RCU register address and bits */ |
| 393 | /***********************************************************************/ |
| 394 | |
| 395 | #define INCA_IP2_RCU (KSEG1+0x1E001C00) |
| 396 | /***********************************************************************/ |
| 397 | |
| 398 | /***Reset Request Register***/ |
| 399 | #define INCA_IP2_RCU_RST_REQ ((volatile u32*)(INCA_IP2_RCU + 0x0000)) |
| 400 | #define INCA_IP2_RCU_RST_REQ_CPU0 (1 << 31) |
| 401 | #define INCA_IP2_RCU_RST_REQ_CPU1 (1 << 30) |
| 402 | #define INCA_IP2_RCU_RST_REQ_CPUSUB (1 << 29) |
| 403 | #define INCA_IP2_RCU_RST_REQ_HRST (1 << 28) |
| 404 | #define INCA_IP2_RCU_RST_REQ_WDT0 (1 << 27) |
| 405 | #define INCA_IP2_RCU_RST_REQ_WDT1 (1 << 26) |
| 406 | #define INCA_IP2_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1)) |
| 407 | #define INCA_IP2_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23) |
| 408 | #define INCA_IP2_RCU_RST_REQ_SWTBOOT (1 << 22) |
| 409 | #define INCA_IP2_RCU_RST_REQ_DMA (1 << 21) |
| 410 | #define INCA_IP2_RCU_RST_REQ_ETHPHY1 (1 << 20) |
| 411 | #define INCA_IP2_RCU_RST_REQ_ETHPHY0 (1 << 19) |
| 412 | #define INCA_IP2_RCU_RST_REQ_CPU0_BR (1 << 18) |
| 413 | |
| 414 | /* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ |
| 415 | #define INCA_IP2_RCU_RST_REQ_ALL 0xFC380000 |
| 416 | |
| 417 | /***Reset Status Register***/ |
| 418 | #define INCA_IP2_RCU_SR ((volatile u32*)(INCA_IP2_RCU + 0x0008)) |
| 419 | |
| 420 | /***NMI Status Register***/ |
| 421 | #define INCA_IP2_RCU_NMISR ((volatile u32*)(INCA_IP2_RCU + 0x00F4)) |
| 422 | #define INCA_IP2_RCU_NMISR_NMIEXT (1 << 2) |
| 423 | #define INCA_IP2_RCU_NMISR_NMIPLL2 (1 << 1) |
| 424 | #define INCA_IP2_RCU_NMISR_NMIPLL1 (1 << 0) |
| 425 | |
| 426 | /***********************************************************************/ |
| 427 | /* Module : EBU register address and bits */ |
| 428 | /***********************************************************************/ |
| 429 | |
| 430 | #define INCA_IP2_EBU (KSEG1+0x14102000) |
| 431 | /***********************************************************************/ |
| 432 | |
| 433 | #define INCA_IP2_EBU_ADDSEL0 ((volatile u32*)(INCA_IP2_EBU + 0x0020)) |
| 434 | #define INCA_IP2_EBU_ADDSEL1 ((volatile u32*)(INCA_IP2_EBU + 0x0024)) |
| 435 | #define INCA_IP2_EBU_ADDSEL2 ((volatile u32*)(INCA_IP2_EBU + 0x0028)) |
| 436 | #define INCA_IP2_EBU_ADDSEL3 ((volatile u32*)(INCA_IP2_EBU + 0x002C)) |
| 437 | #define INCA_IP2_EBU_CON0 ((volatile u32*)(INCA_IP2_EBU + 0x0060)) |
| 438 | #define INCA_IP2_EBU_CON1 ((volatile u32*)(INCA_IP2_EBU + 0x0064)) |
| 439 | #define INCA_IP2_EBU_CON2 ((volatile u32*)(INCA_IP2_EBU + 0x0068)) |
| 440 | #define INCA_IP2_EBU_CON3 ((volatile u32*)(INCA_IP2_EBU + 0x006C)) |
| 441 | #define INCA_IP2_EBU_CON_WRDIS (1 << 31) |
| 442 | |
| 443 | |
| 444 | |
| 445 | |
| 446 | /***********************************************************************/ |
| 447 | /* Module : SWITCH register address and bits */ |
| 448 | /***********************************************************************/ |
| 449 | |
| 450 | #define INCA_IP2_SWITCH (KSEG1+0x18000000) |
| 451 | /***********************************************************************/ |
| 452 | |
| 453 | /* PR Base address */ |
| 454 | #define PR_BASE (INCA_IP2_SWITCH + 0x00008000) |
| 455 | |
| 456 | /* SE Base Address */ |
| 457 | #define SE_BASE (INCA_IP2_SWITCH + 0x00009000) |
| 458 | |
| 459 | #define PR_CTRL_REG (PR_BASE + 0x0000) |
| 460 | #define MA_LEARN_REG (PR_BASE + 0x0004) |
| 461 | #define DST_LOOKUP_REG (PR_BASE + 0x0008) |
| 462 | |
| 463 | #define COS_SEL_REG (PR_BASE + 0x000c) |
| 464 | #define PRI2_COS_REG (PR_BASE + 0x0010) |
| 465 | #define UNKNOWN_DEST_REG (PR_BASE + 0x0014) |
| 466 | |
| 467 | #define CPU_ACS_CTRL_REG (PR_BASE + 0x0018) |
| 468 | #define CPU_ACS_DATA_REG (PR_BASE + 0x001c) |
| 469 | |
| 470 | #define MA_READ_REG (PR_BASE + 0x0020) |
| 471 | #define TB_CTRL_REG (PR_BASE + 0x0024) |
| 472 | #define RATE_REG (PR_BASE + 0x0028) |
| 473 | #define BURST_REG (PR_BASE + 0x0048) |
| 474 | #define EBURST_REG (PR_BASE + 0x0068) |
| 475 | |
| 476 | #define RULE_SEL_REG (PR_BASE + 0x0088) |
| 477 | |
| 478 | #define GEN_SFT_AGE_STB (PR_BASE + 0x008C) |
| 479 | #define PR_ISR_REG (PR_BASE + 0x0090) |
| 480 | #define PR_IMR_REG (PR_BASE + 0x0094) |
| 481 | #define PR_IPR_REG (PR_BASE + 0x0098) |
| 482 | #define BPDU_REG (PR_BASE + 0x00A4) |
| 483 | |
| 484 | /* Switching Engine Register Description */ |
| 485 | #define QLL_CMD_REG (SE_BASE) |
| 486 | #define QLL_DATA_REG0 (SE_BASE + 0x0004) |
| 487 | #define QLL_DATA_REG1 (SE_BASE + 0x0008) |
| 488 | |
| 489 | #define VLAN_MIBS_CMD_REG (SE_BASE + 0x000c) |
| 490 | #define VLAN_MIBS_DATA_REG (SE_BASE + 0x0010) |
| 491 | |
| 492 | #define SD_CMD_REG (SE_BASE + 0x0014) |
| 493 | #define SD_DATA_REGS0 (SE_BASE + 0x0018) |
| 494 | #define SD_DATA_REGS1 (SE_BASE + 0x001C) |
| 495 | #define SD_DATA_REGS2 (SE_BASE + 0x0020) |
| 496 | |
| 497 | #define VLAN_TBL_CMD_REG (SE_BASE + 0x0024) |
| 498 | #define VLAN_TBL_DATA_REG (SE_BASE + 0x0028) |
| 499 | |
| 500 | #define FD_TBL_CMD_REG (SE_BASE + 0x002c) |
| 501 | #define FD_TBL_DATA_REG (SE_BASE + 0x0030) |
| 502 | |
| 503 | #define SYMM_VLAN_REG (SE_BASE + 0x0038) |
| 504 | #define PORT_AUTH (SE_BASE + 0x0048) |
| 505 | #define CPU_LINK_OK_REG (SE_BASE + 0x0050) |
| 506 | /* #define TRUNK_CTRL_REGS (SE_BASE + 0x0054) */ |
| 507 | #define MIRROR_PORT_REG (SE_BASE + 0x0064) |
| 508 | |
| 509 | #define ST_PT_REG (SE_BASE + 0x0068) |
| 510 | #define JUMBO_ENABLE_REG (SE_BASE + 0x006C) |
| 511 | #define STACK_PORT_REG (SE_BASE + 0x0074) |
| 512 | #define EG_MON_REG (SE_BASE + 0x007C) |
| 513 | #define VR_MIB_REG (SE_BASE + 0x0080) |
| 514 | #define QUEUE_CMD_REGS (SE_BASE + 0x0090) |
| 515 | |
| 516 | #define GLOBAL_RX_WM_REG (SE_BASE + 0x0200) |
| 517 | #define PORT0_RX_WM_REG0 (SE_BASE + 0x0204) |
| 518 | #define PORT1_RX_WM_REG0 (SE_BASE + 0x0208) |
| 519 | #define PORT2_RX_WM_REG0 (SE_BASE + 0x020C) |
| 520 | |
| 521 | #define PORT_RX_WM_REGS (SE_BASE + 0x0200) |
| 522 | #define PORT_TX_WM_REGS (SE_BASE + 0x0300) |
| 523 | #define PORT0_TX_WM_REG0 (SE_BASE + 0x0330) |
| 524 | #define PORT1_TX_WM_REG0 (SE_BASE + 0x0338) |
| 525 | #define PORT2_TX_WM_REG0 (SE_BASE + 0x0340) |
| 526 | #define PORT0_TX_WM_REG1 (SE_BASE + 0x0334) |
| 527 | #define PORT1_TX_WM_REG1 (SE_BASE + 0x033C) |
| 528 | #define PORT2_TX_WM_REG1 (SE_BASE + 0x0344) |
| 529 | |
| 530 | |
| 531 | #define QUEUE_STATUS_REGS (SE_BASE + 0x0400) |
| 532 | |
| 533 | #define SE_INT_STS_REG (SE_BASE + 0x08e0) |
| 534 | #define SE_INT_MSK_REG_RD (SE_BASE + 0x08e4) |
| 535 | #define SE_INT_MSK_REG_WR (SE_BASE + 0x08e8) |
| 536 | #define SE_INT_PRI_REG_RD (SE_BASE + 0x08ec) |
| 537 | #define SE_INT_PRI_REG_WR (SE_BASE + 0x08f0) /* address too be defined*/ |
| 538 | |
| 539 | /***********************************************************************/ |
| 540 | /* Module : Ethernet Switch port related addresses and bits */ |
| 541 | /***********************************************************************/ |
| 542 | #define GPORT0_BASE (KSEG1+0x18006000) |
| 543 | #define GPORT1_BASE (KSEG1+0x18007000) |
| 544 | #define GPORT2_BASE (KSEG1+0x1800C000) |
| 545 | |
| 546 | #define PORTREG_BASE GPORT0_BASE |
| 547 | |
| 548 | #define SWITCH_P0_GMAC_REG (GPORT0_BASE + 0x0004) |
| 549 | #define SWITCH_P0_GMAC_CTRL (GPORT0_BASE + 0x000C) |
| 550 | #define SWITCH_P0_RTX_INT_STATUS (GPORT0_BASE + 0x0010) |
| 551 | #define SWITCH_P0_RTX_INT_MASK (GPORT0_BASE + 0x0014) |
| 552 | #define SWITCH_P0_INT_PRIORITY (GPORT0_BASE + 0x0018) |
| 553 | #define SWITCH_P0_RX_CONF (GPORT0_BASE + 0x0400) |
| 554 | #define SWITCH_P0_OFFSET0_REG (GPORT0_BASE + 0x0404) |
| 555 | #define SWITCH_P0_OFFSET1_REG (GPORT0_BASE + 0x0408) |
| 556 | #define SWITCH_P0_PORT_MASK0_REG (GPORT0_BASE + 0x0420) |
| 557 | #define SWITCH_P0_PORT_MASK1_REG (GPORT0_BASE + 0x0424) |
| 558 | #define SWITCH_P0_PORT_MASK2_REG (GPORT0_BASE + 0x0428) |
| 559 | #define SWITCH_P0_PORT_MASK3_REG (GPORT0_BASE + 0x042C) |
| 560 | #define SWITCH_P0_PORT_RULE0_REG (GPORT0_BASE + 0x0430) |
| 561 | #define SWITCH_P0_PORT_RULE1_REG (GPORT0_BASE + 0x0434) |
| 562 | #define SWITCH_P0_PORT_RULE2_REG (GPORT0_BASE + 0x0438) |
| 563 | #define SWITCH_P0_PORT_RULE3_REG (GPORT0_BASE + 0x043C) |
| 564 | #define SWITCH_P0_PORT_IKEY_SEL (GPORT0_BASE + 0x0440) |
| 565 | #define SWITCH_P0_PORT_RX_VLAN_ID (GPORT0_BASE + 0x0450) |
| 566 | #define SWITCH_P0_TX_CONF (GPORT0_BASE + 0x0800) |
| 567 | #define SWITCH_P0_PORT_TX_VLAN_ID (GPORT0_BASE + 0x0804) |
| 568 | #define SWITCH_P0_PORT_MIB_REG_0 (GPORT0_BASE + 0x0C00) |
| 569 | #define SWITCH_P0_GMAC_MIB_REG_0 (GPORT0_BASE + 0x0C54) |
| 570 | |
| 571 | #define SWITCH_P1_GMAC_REG (GPORT1_BASE + 0x0004) |
| 572 | #define SWITCH_P1_GMAC_CTRL (GPORT1_BASE + 0x000C) |
| 573 | #define SWITCH_P1_RTX_INT_STATUS (GPORT1_BASE + 0x0010) |
| 574 | #define SWITCH_P1_RTX_INT_MASK (GPORT1_BASE + 0x0014) |
| 575 | #define SWITCH_P1_INT_PRIORITY (GPORT1_BASE + 0x0018) |
| 576 | #define SWITCH_P1_RX_CONF (GPORT1_BASE + 0x0400) |
| 577 | #define SWITCH_P1_OFFSET0_REG (GPORT1_BASE + 0x0404) |
| 578 | #define SWITCH_P1_OFFSET1_REG (GPORT1_BASE + 0x0408) |
| 579 | #define SWITCH_P1_PORT_MASK0_REG (GPORT1_BASE + 0x0420) |
| 580 | #define SWITCH_P1_PORT_MASK1_REG (GPORT1_BASE + 0x0424) |
| 581 | #define SWITCH_P1_PORT_MASK2_REG (GPORT1_BASE + 0x0428) |
| 582 | #define SWITCH_P1_PORT_MASK3_REG (GPORT1_BASE + 0x042C) |
| 583 | #define SWITCH_P1_PORT_RULE0_REG (GPORT1_BASE + 0x0430) |
| 584 | #define SWITCH_P1_PORT_RULE1_REG (GPORT1_BASE + 0x0434) |
| 585 | #define SWITCH_P1_PORT_RULE2_REG (GPORT1_BASE + 0x0438) |
| 586 | #define SWITCH_P1_PORT_RULE3_REG (GPORT1_BASE + 0x043C) |
| 587 | #define SWITCH_P1_PORT_IKEY_SEL (GPORT1_BASE + 0x0440) |
| 588 | #define SWITCH_P1_PORT_RX_VLAN_ID (GPORT1_BASE + 0x0450) |
| 589 | #define SWITCH_P1_TX_CONF (GPORT1_BASE + 0x0800) |
| 590 | #define SWITCH_P1_PORT_TX_VLAN_ID (GPORT1_BASE + 0x0804) |
| 591 | #define SWITCH_P1_PORT_MIB_REG_0 (GPORT1_BASE + 0x0C00) |
| 592 | #define SWITCH_P1_GMAC_MIB_REG_0 (GPORT1_BASE + 0x0C54) |
| 593 | |
| 594 | #define SWITCH_P2_GMAC_REG (GPORT2_BASE + 0x0004) |
| 595 | #define SWITCH_P2_GMAC_CTRL (GPORT2_BASE + 0x000C) |
| 596 | #define SWITCH_P2_RTX_INT_STATUS (GPORT2_BASE + 0x0010) |
| 597 | #define SWITCH_P2_RTX_INT_MASK (GPORT2_BASE + 0x0014) |
| 598 | #define SWITCH_P2_INT_PRIORITY (GPORT2_BASE + 0x0018) |
| 599 | #define SWITCH_P2_MDIO_ID_1 (GPORT2_BASE + 0x00A8) |
| 600 | #define SWITCH_P2_PAUSE_CTL_1 (GPORT2_BASE + 0x00B0) |
| 601 | #define SWITCH_P2_MDIO_MOD_SEL (GPORT2_BASE + 0x00B4) |
| 602 | #define SWITCH_P2_MDIO_ACC_0 (GPORT2_BASE + 0x00B8) |
| 603 | #define SWITCH_P2_RX_CONF (GPORT2_BASE + 0x0400) |
| 604 | #define SWITCH_P2_OFFSET0_REG (GPORT2_BASE + 0x0404) |
| 605 | #define SWITCH_P2_OFFSET1_REG (GPORT2_BASE + 0x0408) |
| 606 | #define SWITCH_P2_PORT_MASK0_REG (GPORT2_BASE + 0x0420) |
| 607 | #define SWITCH_P2_PORT_MASK1_REG (GPORT2_BASE + 0x0424) |
| 608 | #define SWITCH_P2_PORT_MASK2_REG (GPORT2_BASE + 0x0428) |
| 609 | #define SWITCH_P2_PORT_MASK3_REG (GPORT2_BASE + 0x042C) |
| 610 | #define SWITCH_P2_PORT_RULE0_REG (GPORT2_BASE + 0x0430) |
| 611 | #define SWITCH_P2_PORT_RULE1_REG (GPORT2_BASE + 0x0434) |
| 612 | #define SWITCH_P2_PORT_RULE2_REG (GPORT2_BASE + 0x0438) |
| 613 | #define SWITCH_P2_PORT_RULE3_REG (GPORT2_BASE + 0x043C) |
| 614 | #define SWITCH_P2_PORT_IKEY_SEL (GPORT2_BASE + 0x0440) |
| 615 | #define SWITCH_P2_PORT_RX_VLAN_ID (GPORT2_BASE + 0x0450) |
| 616 | #define SWITCH_P2_TX_CONF (GPORT2_BASE + 0x0800) |
| 617 | #define SWITCH_P2_PORT_TX_VLAN_ID (GPORT2_BASE + 0x0804) |
| 618 | #define SWITCH_P2_PORT_MIB_REG_0 (GPORT2_BASE + 0x0C00) |
| 619 | #define SWITCH_P2_GMAC_MIB_REG_0 (GPORT2_BASE + 0x0C54) |
| 620 | |
| 621 | #define MDIO_MOD_SEL SWITCH_P2_MDIO_MOD_SEL |
| 622 | #define SWITCH_MDIO_ACC SWITCH_P2_MDIO_ACC_0 |
| 623 | #define SWITCH_MDIO_ID SWITCH_P2_MDIO_ID_1 |
| 624 | /* #define TX_CONFIG_REG SWITCH_P0_TX_CONF */ |
| 625 | |
| 626 | #define SWITCH_PMAC_HD_CTL (GPORT2_BASE + 0x0070) |
| 627 | #define SWITCH_PMAC_SA1 (GPORT2_BASE + 0x0074) |
| 628 | #define SWITCH_PMAC_SA2 (GPORT2_BASE + 0x0078) |
| 629 | #define SWITCH_PMAC_DA1 (GPORT2_BASE + 0x007C) |
| 630 | #define SWITCH_PMAC_DA2 (GPORT2_BASE + 0x0080) |
| 631 | #define SWITCH_PMAC_VLAN (GPORT2_BASE + 0x0084) |
| 632 | #define SWITCH_PMAC_TX_IPG (GPORT2_BASE + 0x0088) |
| 633 | #define SWITCH_PMAC_RX_IPG (GPORT2_BASE + 0x008C) |
| 634 | |
| 635 | |
