Root/package/uboot-lantiq/files/board/infineon/easy50712/danube.c

1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2010
6 * Thomas Langer, Ralph Hempel
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <command.h>
29#include <netdev.h>
30#include <miiphy.h>
31#include <asm/addrspace.h>
32#include <asm/danube.h>
33#include <asm/reboot.h>
34#include <asm/io.h>
35#if defined(CONFIG_CMD_HTTPD)
36#include <httpd.h>
37#endif
38
39extern ulong ifx_get_ddr_hz(void);
40extern ulong ifx_get_cpuclk(void);
41
42/* definitions for external PHYs / Switches */
43/* Split values into phy address and register address */
44#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
45
46/* IDs and registers of known external switches */
47#define ID_SAMURAI_0 0x1020
48#define ID_SAMURAI_1 0x0007
49#define SAMURAI_ID_REG0 0xA0
50#define SAMURAI_ID_REG1 0xA1
51
52#define ID_TANTOS 0x2599
53
54void _machine_restart(void)
55{
56    *DANUBE_RCU_RST_REQ |=1<<30;
57}
58
59#ifdef CONFIG_SYS_RAMBOOT
60phys_size_t initdram(int board_type)
61{
62    return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
63}
64#elif defined(CONFIG_USE_DDR_RAM)
65phys_size_t initdram(int board_type)
66{
67    return (CONFIG_SYS_MAX_RAM);
68}
69#else
70
71static ulong max_sdram_size(void) /* per Chip Select */
72{
73    /* The only supported SDRAM data width is 16bit.
74     */
75#define CFG_DW 4
76
77    /* The only supported number of SDRAM banks is 4.
78     */
79#define CFG_NB 4
80
81    ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
82    int cols = cfgpb0 & 0xF;
83    int rows = (cfgpb0 & 0xF0) >> 4;
84    ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
85
86    return size;
87}
88
89/*
90 * Check memory range for valid RAM. A simple memory test determines
91 * the actually available RAM size between addresses `base' and
92 * `base + maxsize'.
93 */
94
95static long int dram_size(long int *base, long int maxsize)
96{
97    volatile long int *addr;
98    ulong cnt, val;
99    ulong save[32]; /* to make test non-destructive */
100    unsigned char i = 0;
101
102    for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
103        addr = base + cnt; /* pointer arith! */
104
105        save[i++] = *addr;
106        *addr = ~cnt;
107    }
108
109    /* write 0 to base address */
110    addr = base;
111    save[i] = *addr;
112    *addr = 0;
113
114    /* check at base address */
115    if ((val = *addr) != 0) {
116        *addr = save[i];
117        return (0);
118    }
119
120    for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
121        addr = base + cnt; /* pointer arith! */
122
123        val = *addr;
124        *addr = save[--i];
125
126        if (val != (~cnt)) {
127            return (cnt * sizeof (long));
128        }
129    }
130    return (maxsize);
131}
132
133phys_size_t initdram(int board_type)
134{
135    int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
136    ulong size, max_size = 0;
137    ulong our_address;
138
139    /* load t9 into our_address */
140    asm volatile ("move %0, $25" : "=r" (our_address) :);
141
142    /* Can't probe for RAM size unless we are running from Flash.
143     * find out whether running from DRAM or Flash.
144     */
145    if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
146    {
147        return max_sdram_size();
148    }
149
150    for (cols = 0x8; cols <= 0xC; cols++)
151    {
152        for (rows = 0xB; rows <= 0xD; rows++)
153        {
154            *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
155                                      (rows << 4) | cols;
156            size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
157                                      max_sdram_size());
158
159            if (size > max_size)
160            {
161                best_val = *DANUBE_SDRAM_MC_CFGPB0;
162                max_size = size;
163            }
164        }
165    }
166
167    *DANUBE_SDRAM_MC_CFGPB0 = best_val;
168    return max_size;
169}
170#endif
171
172int checkboard (void)
173{
174    unsigned long chipid = *DANUBE_MPS_CHIPID;
175    int part_num;
176
177    puts ("Board: ");
178
179    part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
180    switch (part_num)
181    {
182    case 0x129:
183    case 0x12D:
184        puts("Danube/Twinpass/Vinax-VE ");
185        break;
186    default:
187        printf ("unknown, chip part number 0x%03X ", part_num);
188        break;
189    }
190    printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
191
192    printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
193    printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
194
195    return 0;
196}
197
198#ifdef CONFIG_SKIP_LOWLEVEL_INIT
199int board_early_init_f(void)
200{
201#ifdef CONFIG_EBU_ADDSEL0
202    (*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
203#endif
204#ifdef CONFIG_EBU_ADDSEL1
205    (*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
206#endif
207#ifdef CONFIG_EBU_ADDSEL2
208    (*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
209#endif
210#ifdef CONFIG_EBU_ADDSEL3
211    (*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
212#endif
213#ifdef CONFIG_EBU_BUSCON0
214    (*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
215#endif
216#ifdef CONFIG_EBU_BUSCON1
217    (*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
218#endif
219#ifdef CONFIG_EBU_BUSCON2
220    (*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
221#endif
222#ifdef CONFIG_EBU_BUSCON3
223    (*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
224#endif
225
226    return 0;
227}
228#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
229
230#ifdef CONFIG_EXTRA_SWITCH
231static int external_switch_init(void)
232{
233    unsigned short chipid0=0xdead, chipid1=0xbeef;
234    static char * const name = "lq_cpe_eth";
235
236#ifdef CLK_OUT2_25MHZ
237    *DANUBE_GPIO_P0_DIR=0x0000ae78;
238    *DANUBE_GPIO_P0_ALTSEL0=0x00008078;
239    //joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080;
240    *DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1
241    *DANUBE_CGU_IFCCR=0x00400010;
242    *DANUBE_GPIO_P0_OD=0x0000ae78;
243#endif
244
245    /* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */
246    udelay(100000);
247
248    debug("\nsearching for Samurai switch ... ");
249    if ( (miiphy_read(name, PHYADDR(SAMURAI_ID_REG0), &chipid0)==0) &&
250         (miiphy_read(name, PHYADDR(SAMURAI_ID_REG1), &chipid1)==0) ) {
251        if (((chipid0 & 0xFFF0) == ID_SAMURAI_0) &&
252            ((chipid1 & 0x000F) == ID_SAMURAI_1)) {
253            debug("found");
254
255            /* enable "Crossover Auto Detect" + defaults */
256            /* P0 */
257            miiphy_write(name, PHYADDR(0x01), 0x840F);
258            /* P1 */
259            miiphy_write(name, PHYADDR(0x03), 0x840F);
260            /* P2 */
261            miiphy_write(name, PHYADDR(0x05), 0x840F);
262            /* P3 */
263            miiphy_write(name, PHYADDR(0x07), 0x840F);
264            /* P4 */
265            miiphy_write(name, PHYADDR(0x08), 0x840F);
266            /* P5 */
267            miiphy_write(name, PHYADDR(0x09), 0x840F);
268            /* System Control 4: CPU on port 1 and other */
269            miiphy_write(name, PHYADDR(0x12), 0x3602);
270            #ifdef CLK_OUT2_25MHZ
271            /* Bandwidth Control Enable Register: enable */
272            miiphy_write(name, PHYADDR(0x33), 0x4000);
273            #endif
274        }
275    }
276
277    debug("\nsearching for TANTOS switch ... ");
278    if (miiphy_read(name, PHYADDR(0x101), &chipid0) == 0) {
279        if (chipid0 == ID_TANTOS) {
280            debug("found");
281
282            /* P5 Basic Control: Force Link Up */
283            miiphy_write(name, PHYADDR(0xA1), 0x0004);
284            /* P6 Basic Control: Force Link Up */
285            miiphy_write(name, PHYADDR(0xC1), 0x0004);
286            /* RGMII/MII Port Control (P4/5/6) */
287            miiphy_write(name, PHYADDR(0xF5), 0x0773);
288
289            /* Software workaround. */
290            /* PHY reset from P0 to P4. */
291
292            /* set data for indirect write */
293            miiphy_write(name, PHYADDR(0x121), 0x8000);
294
295            /* P0 */
296            miiphy_write(name, PHYADDR(0x120), 0x0400);
297            udelay(1000);
298            /* P1 */
299            miiphy_write(name, PHYADDR(0x120), 0x0420);
300            udelay(1000);
301            /* P2 */
302            miiphy_write(name, PHYADDR(0x120), 0x0440);
303            udelay(1000);
304            /* P3 */
305            miiphy_write(name, PHYADDR(0x120), 0x0460);
306            udelay(1000);
307            /* P4 */
308            miiphy_write(name, PHYADDR(0x120), 0x0480);
309            udelay(1000);
310        }
311    }
312    debug("\n");
313
314    return 0;
315}
316#endif /* CONFIG_EXTRA_SWITCH */
317
318int board_eth_init(bd_t *bis)
319{
320#if defined(CONFIG_IFX_ETOP)
321
322    *DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
323    *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
324
325    if (lq_eth_initialize(bis)<0)
326        return -1;
327
328    *DANUBE_RCU_RST_REQ |=1;
329    udelay(200000);
330    *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
331    udelay(1000);
332
333#ifdef CONFIG_EXTRA_SWITCH
334    if (external_switch_init()<0)
335        return -1;
336#endif /* CONFIG_EXTRA_SWITCH */
337#endif /* CONFIG_IFX_ETOP */
338
339    return 0;
340}
341
342#if defined(CONFIG_CMD_HTTPD)
343int do_http_upgrade(const unsigned char *data, const ulong size)
344{
345    char buf[128];
346
347    if(getenv ("ram_addr") == NULL)
348        return -1;
349    if(getenv ("kernel_addr") == NULL)
350        return -1;
351    /* check the image */
352    if(run_command("imi ${ram_addr}", 0) < 0) {
353        return -1;
354    }
355    /* write the image to the flash */
356    puts("http ugrade ...\n");
357    sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size);
358    return run_command(buf, 0);
359}
360
361int do_http_progress(const int state)
362{
363    /* toggle LED's here */
364    switch(state) {
365        case HTTP_PROGRESS_START:
366        puts("http start\n");
367        break;
368        case HTTP_PROGRESS_TIMEOUT:
369        puts(".");
370        break;
371        case HTTP_PROGRESS_UPLOAD_READY:
372        puts("http upload ready\n");
373        break;
374        case HTTP_PROGRESS_UGRADE_READY:
375        puts("http ugrade ready\n");
376        break;
377        case HTTP_PROGRESS_UGRADE_FAILED:
378        puts("http ugrade failed\n");
379        break;
380    }
381    return 0;
382}
383
384unsigned long do_http_tmp_address(void)
385{
386    char *s = getenv ("ram_addr");
387    if (s) {
388        ulong tmp = simple_strtoul (s, NULL, 16);
389        return tmp;
390    }
391    return 0 /*0x80a00000*/;
392}
393
394#endif
395

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