| 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <command.h> |
| 26 | #include <netdev.h> |
| 27 | #include <asm/mipsregs.h> |
| 28 | #include <asm/cacheops.h> |
| 29 | #include <asm/reboot.h> |
| 30 | #include <asm/jz4740.h> |
| 31 | |
| 32 | #if !defined (CONFIG_NAND_SPL) && !defined (CONFIG_MSC_SPL) |
| 33 | |
| 34 | #define cache_op(op,addr) \ |
| 35 | __asm__ __volatile__( \ |
| 36 | " .set push \n" \ |
| 37 | " .set noreorder \n" \ |
| 38 | " .set mips3\n\t \n" \ |
| 39 | " cache %0, %1 \n" \ |
| 40 | " .set pop \n" \ |
| 41 | : \ |
| 42 | : "i" (op), "R" (*(unsigned char *)(addr))) |
| 43 | |
| 44 | void __attribute__((weak)) _machine_restart(void) |
| 45 | { |
| 46 | __wdt_select_extalclk(); |
| 47 | __wdt_select_clk_div64(); |
| 48 | __wdt_set_data(100); |
| 49 | __wdt_set_count(0); |
| 50 | __tcu_start_wdt_clock(); |
| 51 | __wdt_start(); |
| 52 | while(1); |
| 53 | #if defined(CONFIG_JzRISC) |
| 54 | void (*f)(void) = (void *) 0xbfc00000; |
| 55 | f(); |
| 56 | #endif |
| 57 | } |
| 58 | |
| 59 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
| 60 | { |
| 61 | _machine_restart(); |
| 62 | |
| 63 | fprintf(stderr, "*** reset failed ***\n"); |
| 64 | return 0; |
| 65 | } |
| 66 | |
| 67 | void flush_cache(ulong start_addr, ulong size) |
| 68 | { |
| 69 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; |
| 70 | unsigned long addr = start_addr & ~(lsize - 1); |
| 71 | unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); |
| 72 | |
| 73 | while (1) { |
| 74 | cache_op(Hit_Writeback_Inv_D, addr); |
| 75 | cache_op(Hit_Invalidate_I, addr); |
| 76 | if (addr == aend) |
| 77 | break; |
| 78 | addr += lsize; |
| 79 | } |
| 80 | } |
| 81 | |
| 82 | void flush_dcache_range(ulong start_addr, ulong stop) |
| 83 | { |
| 84 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; |
| 85 | unsigned long addr = start_addr & ~(lsize - 1); |
| 86 | unsigned long aend = (stop - 1) & ~(lsize - 1); |
| 87 | |
| 88 | while (1) { |
| 89 | cache_op(Hit_Writeback_Inv_D, addr); |
| 90 | if (addr == aend) |
| 91 | break; |
| 92 | addr += lsize; |
| 93 | } |
| 94 | } |
| 95 | |
| 96 | void invalidate_dcache_range(ulong start_addr, ulong stop) |
| 97 | { |
| 98 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; |
| 99 | unsigned long addr = start_addr & ~(lsize - 1); |
| 100 | unsigned long aend = (stop - 1) & ~(lsize - 1); |
| 101 | |
| 102 | while (1) { |
| 103 | cache_op(Hit_Invalidate_D, addr); |
| 104 | if (addr == aend) |
| 105 | break; |
| 106 | addr += lsize; |
| 107 | } |
| 108 | } |
| 109 | |
| 110 | void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) |
| 111 | { |
| 112 | write_c0_entrylo0(low0); |
| 113 | write_c0_pagemask(pagemask); |
| 114 | write_c0_entrylo1(low1); |
| 115 | write_c0_entryhi(hi); |
| 116 | write_c0_index(index); |
| 117 | tlb_write_indexed(); |
| 118 | } |
| 119 | |
| 120 | #endif /* !CONFIG_NAND_SPL !CONFIG_MSC_SPL */ |
| 121 | |
| 122 | void flush_icache_all(void) |
| 123 | { |
| 124 | u32 addr, t = 0; |
| 125 | |
| 126 | asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ |
| 127 | asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ |
| 128 | |
| 129 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; |
| 130 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
| 131 | asm volatile ( |
| 132 | ".set mips3\n\t" |
| 133 | " cache %0, 0(%1)\n\t" |
| 134 | ".set mips2\n\t" |
| 135 | : |
| 136 | : "I" (Index_Store_Tag_I), "r"(addr)); |
| 137 | } |
| 138 | |
| 139 | /* invalicate btb */ |
| 140 | asm volatile ( |
| 141 | ".set mips32\n\t" |
| 142 | "mfc0 %0, $16, 7\n\t" |
| 143 | "nop\n\t" |
| 144 | "ori %0,2\n\t" |
| 145 | "mtc0 %0, $16, 7\n\t" |
| 146 | ".set mips2\n\t" |
| 147 | : |
| 148 | : "r" (t)); |
| 149 | } |
| 150 | |
| 151 | void flush_dcache_all(void) |
| 152 | { |
| 153 | u32 addr; |
| 154 | |
| 155 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; |
| 156 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
| 157 | asm volatile ( |
| 158 | ".set mips3\n\t" |
| 159 | " cache %0, 0(%1)\n\t" |
| 160 | ".set mips2\n\t" |
| 161 | : |
| 162 | : "I" (Index_Writeback_Inv_D), "r"(addr)); |
| 163 | } |
| 164 | |
| 165 | asm volatile ("sync"); |
| 166 | } |
| 167 | |
| 168 | void flush_cache_all(void) |
| 169 | { |
| 170 | flush_dcache_all(); |
| 171 | flush_icache_all(); |
| 172 | } |
| 173 | |
