Root/package/uboot-xburst/files/arch/mips/cpu/xburst/start_spl.S

1/*
2 * Startup Code for MIPS32 XBURST CPU-core
3 *
4 * Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 3 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24    
25#include <config.h>
26#include <version.h>
27#include <asm/regdef.h>
28#include <asm/mipsregs.h>
29#include <asm/addrspace.h>
30#include <asm/cacheops.h>
31
32#include <asm/jz4740.h>
33
34    .set noreorder
35    
36    .globl _start
37    .text
38_start:
39    .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
40reset:
41    /*
42     * STATUS register
43     * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
44     */
45    li t0, 0x0040FC04
46    mtc0 t0, CP0_STATUS
47    /* CAUSE register
48     * IV=1, use the specical interrupt vector (0x200) */
49    li t1, 0x00800000
50    mtc0 t1, CP0_CAUSE
51    
52    bal 1f
53    nop
54    .word _GLOBAL_OFFSET_TABLE_
551:
56    move gp, ra
57    lw t1, 0(ra)
58    move gp, t1
59
60    la sp, 0x80004000
61    la t9, nand_boot
62    j t9
63    nop
64

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