| 1 | /* |
| 2 | * for jz4740 usb boot |
| 3 | * |
| 4 | * Copyright (c) 2009 Author: <jlwei@ingenic.cn> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | .set noreorder |
| 25 | .globl usb_boot |
| 26 | .text |
| 27 | |
| 28 | //---------------------------------------------------------------------- |
| 29 | // Both NAND and USB boot load data to D-Cache first, then transfer |
| 30 | // data from D-Cache to I-Cache, and jump to execute the code in I-Cache. |
| 31 | // So init caches first and then dispatch to a proper boot routine. |
| 32 | //---------------------------------------------------------------------- |
| 33 | |
| 34 | .macro load_addr reg addr |
| 35 | li \reg, 0x80000000 |
| 36 | addiu \reg, \reg, \addr |
| 37 | la $2, usbboot_begin |
| 38 | subu \reg, \reg, $2 |
| 39 | .endm |
| 40 | |
| 41 | usb_boot: |
| 42 | //-------------------------------------------------------------- |
| 43 | // Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz. |
| 44 | //-------------------------------------------------------------- |
| 45 | la $9, 0xB0000000 // CPCCR: Clock Control Register |
| 46 | la $8, 0x42041110 // I:S:M:P=1:2:2:2 |
| 47 | sw $8, 0($9) |
| 48 | |
| 49 | la $9, 0xB0000010 // CPPCR: PLL Control Register |
| 50 | la $8, 0x06000120 // M=12 N=0 D=0 CLK=12*(M+2)/(N+2) |
| 51 | sw $8, 0($9) |
| 52 | |
| 53 | mtc0 $0, $26 // CP0_ERRCTL, restore WST reset state |
| 54 | nop |
| 55 | |
| 56 | mtc0 $0, $16 // CP0_CONFIG |
| 57 | nop |
| 58 | |
| 59 | // Relocate code to beginning of the ram |
| 60 | |
| 61 | la $2, usbboot_begin |
| 62 | la $3, usbboot_end |
| 63 | li $4, 0x80000000 |
| 64 | |
| 65 | 1: |
| 66 | lw $5, 0($2) |
| 67 | sw $5, 0($4) |
| 68 | addiu $2, $2, 4 |
| 69 | bne $2, $3, 1b |
| 70 | addiu $4, $4, 4 |
| 71 | |
| 72 | li $2, 0x80000000 |
| 73 | ori $3, $2, 0 |
| 74 | addiu $3, $3, usbboot_end |
| 75 | la $4, usbboot_begin |
| 76 | subu $3, $3, $4 |
| 77 | |
| 78 | |
| 79 | 2: |
| 80 | cache 0x0, 0($2) // Index_Invalidate_I |
| 81 | cache 0x1, 0($2) // Index_Writeback_Inv_D |
| 82 | addiu $2, $2, 32 |
| 83 | subu $4, $3, $2 |
| 84 | bgtz $4, 2b |
| 85 | nop |
| 86 | |
| 87 | load_addr $3, usb_boot_return |
| 88 | |
| 89 | jr $3 |
| 90 | |
| 91 | usbboot_begin: |
| 92 | |
| 93 | init_caches: |
| 94 | li $2, 3 // cacheable for kseg0 access |
| 95 | mtc0 $2, $16 // CP0_CONFIG |
| 96 | nop |
| 97 | |
| 98 | li $2, 0x20000000 // enable idx-store-data cache insn |
| 99 | mtc0 $2, $26 // CP0_ERRCTL |
| 100 | |
| 101 | ori $2, $28, 0 // start address |
| 102 | ori $3, $2, 0x3fe0 // end address, total 16KB |
| 103 | mtc0 $0, $28, 0 // CP0_TAGLO |
| 104 | mtc0 $0, $28, 1 // CP0_DATALO |
| 105 | cache_clear_a_line: |
| 106 | cache 0x8, 0($2) // Index_Store_Tag_I |
| 107 | cache 0x9, 0($2) // Index_Store_Tag_D |
| 108 | bne $2, $3, cache_clear_a_line |
| 109 | addiu $2, $2, 32 // increment CACHE_LINE_SIZE |
| 110 | |
| 111 | ori $2, $28, 0 // start address |
| 112 | ori $3, $2, 0x3fe0 // end address, total 16KB |
| 113 | la $4, 0x1ffff000 // physical address and 4KB page mask |
| 114 | cache_alloc_a_line: |
| 115 | and $5, $2, $4 |
| 116 | ori $5, $5, 1 // V bit of the physical tag |
| 117 | mtc0 $5, $28, 0 // CP0_TAGLO |
| 118 | cache 0x8, 0($2) // Index_Store_Tag_I |
| 119 | cache 0x9, 0($2) // Index_Store_Tag_D |
| 120 | bne $2, $3, cache_alloc_a_line |
| 121 | addiu $2, $2, 32 // increment CACHE_LINE_SIZE |
| 122 | |
| 123 | nop |
| 124 | nop |
| 125 | nop |
| 126 | //-------------------------------------------------------------- |
| 127 | // Transfer data from dcache to icache, then jump to icache. |
| 128 | // |
| 129 | // Input parameters: |
| 130 | // |
| 131 | // $19: data length in bytes |
| 132 | // $20: jump target address |
| 133 | //-------------------------------------------------------------- |
| 134 | xfer_d2i: |
| 135 | |
| 136 | ori $8, $20, 0 |
| 137 | addu $9, $8, $19 // total 16KB |
| 138 | |
| 139 | 1: |
| 140 | cache 0x0, 0($8) // Index_Invalidate_I |
| 141 | cache 0x1, 0($8) // Index_Writeback_Inv_D |
| 142 | bne $8, $9, 1b |
| 143 | addiu $8, $8, 32 |
| 144 | |
| 145 | // flush write-buffer |
| 146 | sync |
| 147 | |
| 148 | // Invalidate BTB |
| 149 | mfc0 $8, $16, 7 // CP0_CONFIG |
| 150 | nop |
| 151 | ori $8, 2 |
| 152 | mtc0 $8, $16, 7 |
| 153 | nop |
| 154 | |
| 155 | // Overwrite config to disable ram initalisation |
| 156 | li $2, 0xff |
| 157 | sb $2, 20($20) |
| 158 | |
| 159 | jalr $20 |
| 160 | nop |
| 161 | |
| 162 | icache_return: |
| 163 | //-------------------------------------------------------------- |
| 164 | // User code can return to here after executing itself in |
| 165 | // icache, by jumping to $31. |
| 166 | //-------------------------------------------------------------- |
| 167 | b usb_boot_return |
| 168 | nop |
| 169 | |
| 170 | |
| 171 | usb_boot_return: |
| 172 | //-------------------------------------------------------------- |
| 173 | // Enable the USB PHY |
| 174 | //-------------------------------------------------------------- |
| 175 | la $9, 0xB0000024 // CPM_SCR |
| 176 | lw $8, 0($9) |
| 177 | ori $8, 0x40 // USBPHY_ENABLE |
| 178 | sw $8, 0($9) |
| 179 | |
| 180 | //-------------------------------------------------------------- |
| 181 | // Initialize USB registers |
| 182 | //-------------------------------------------------------------- |
| 183 | la $27, 0xb3040000 // USB registers base address |
| 184 | |
| 185 | sb $0, 0x0b($27) // INTRUSBE: disable common USB interrupts |
| 186 | sh $0, 0x06($27) // INTRINE: disable EPIN interrutps |
| 187 | sh $0, 0x08($27) // INTROUTE: disable EPOUT interrutps |
| 188 | |
| 189 | li $9, 0x61 |
| 190 | sb $9, 0x01($27) // POWER: HSENAB | SUSPENDM | SOFTCONN |
| 191 | |
| 192 | //-------------------------------------------------------------- |
| 193 | // Initialize USB states |
| 194 | //-------------------------------------------------------------- |
| 195 | li $22, 0 // set EP0 to IDLE state |
| 196 | li $23, 1 // no data stage |
| 197 | |
| 198 | //-------------------------------------------------------------- |
| 199 | // Main loop of polling the usb commands |
| 200 | //-------------------------------------------------------------- |
| 201 | usb_command_loop: |
| 202 | lbu $9, 0x0a($27) // read INTRUSB |
| 203 | andi $9, 0x04 // check USB_INTR_RESET |
| 204 | beqz $9, check_intr_ep0in |
| 205 | nop |
| 206 | |
| 207 | //-------------------------------------------------------------- |
| 208 | // 1. Handle USB reset interrupt |
| 209 | //-------------------------------------------------------------- |
| 210 | handle_reset_intr: |
| 211 | lbu $9, 0x01($27) // read POWER |
| 212 | andi $9, 0x10 // test HS_MODE |
| 213 | bnez $9, _usb_set_maxpktsize |
| 214 | li $9, 512 // max packet size of HS mode |
| 215 | li $9, 64 // max packet size of FS mode |
| 216 | |
| 217 | _usb_set_maxpktsize: |
| 218 | li $8, 1 |
| 219 | sb $8, 0x0e($27) // set INDEX 1 |
| 220 | |
| 221 | sh $9, 0x10($27) // INMAXP |
| 222 | sb $0, 0x13($27) // INCSRH |
| 223 | sh $9, 0x14($27) // OUTMAXP |
| 224 | sb $0, 0x17($27) // OUTCSRH |
| 225 | |
| 226 | _usb_flush_fifo: |
| 227 | li $8, 0x48 // INCSR_CDT && INCSR_FF |
| 228 | sb $8, 0x12($27) // INCSR |
| 229 | li $8, 0x90 // OUTCSR_CDT && OUTCSR_FF |
| 230 | sb $8, 0x16($27) // OUTCSR |
| 231 | |
| 232 | li $22, 0 // set EP0 to IDLE state |
| 233 | li $23, 1 // no data stage |
| 234 | |
| 235 | //-------------------------------------------------------------- |
| 236 | // 2. Check and handle EP0 interrupt |
| 237 | //-------------------------------------------------------------- |
| 238 | check_intr_ep0in: |
| 239 | lhu $10, 0x02($27) // read INTRIN |
| 240 | andi $9, $10, 0x1 // check EP0 interrupt |
| 241 | beqz $9, check_intr_ep1in |
| 242 | nop |
| 243 | |
| 244 | handle_ep0_intr: |
| 245 | sb $0, 0x0e($27) // set INDEX 0 |
| 246 | lbu $11, 0x12($27) // read CSR0 |
| 247 | |
| 248 | andi $9, $11, 0x04 // check SENTSTALL |
| 249 | beqz $9, _ep0_setupend |
| 250 | nop |
| 251 | |
| 252 | _ep0_sentstall: |
| 253 | andi $9, $11, 0xdb |
| 254 | sb $9, 0x12($27) // clear SENDSTALL and SENTSTALL |
| 255 | li $22, 0 // set EP0 to IDLE state |
| 256 | |
| 257 | _ep0_setupend: |
| 258 | andi $9, $11, 0x10 // check SETUPEND |
| 259 | beqz $9, ep0_idle_state |
| 260 | nop |
| 261 | |
| 262 | ori $9, $11, 0x80 |
| 263 | sb $9, 0x12($27) // set SVDSETUPEND |
| 264 | li $22, 0 // set EP0 to IDLE state |
| 265 | |
| 266 | ep0_idle_state: |
| 267 | bnez $22, ep0_tx_state |
| 268 | nop |
| 269 | |
| 270 | //-------------------------------------------------------------- |
| 271 | // 2.1 Handle EP0 IDLE state interrupt |
| 272 | //-------------------------------------------------------------- |
| 273 | andi $9, $11, 0x01 // check OUTPKTRDY |
| 274 | beqz $9, check_intr_ep1in |
| 275 | nop |
| 276 | |
| 277 | //-------------------------------------------------------------- |
| 278 | // Read 8-bytes setup packet from the FIFO |
| 279 | //-------------------------------------------------------------- |
| 280 | lw $25, 0x20($27) // first word of setup packet |
| 281 | lw $26, 0x20($27) // second word of setup packet |
| 282 | |
| 283 | andi $9, $25, 0x60 // bRequestType & USB_TYPE_MASK |
| 284 | beqz $9, _ep0_std_req |
| 285 | nop |
| 286 | |
| 287 | //-------------------------------------------------------------- |
| 288 | // 2.1.1 Vendor-specific setup request |
| 289 | //-------------------------------------------------------------- |
| 290 | _ep0_vend_req: |
| 291 | li $22, 0 // set EP0 to IDLE state |
| 292 | li $23, 1 // NoData = 1 |
| 293 | |
| 294 | andi $9, $25, 0xff00 // check bRequest |
| 295 | srl $9, $9, 8 |
| 296 | beqz $9, __ep0_get_cpu_info |
| 297 | sub $8, $9, 0x1 |
| 298 | beqz $8, __ep0_set_data_address |
| 299 | sub $8, $9, 0x2 |
| 300 | beqz $8, __ep0_set_data_length |
| 301 | sub $8, $9, 0x3 |
| 302 | beqz $8, __ep0_flush_caches |
| 303 | sub $8, $9, 0x4 |
| 304 | beqz $8, __ep0_prog_start1 |
| 305 | sub $8, $9, 0x5 |
| 306 | beqz $8, __ep0_prog_start2 |
| 307 | nop |
| 308 | b _ep0_idle_state_fini // invalid request |
| 309 | nop |
| 310 | |
| 311 | __ep0_get_cpu_info: |
| 312 | load_addr $20, cpu_info_data // data pointer to transfer |
| 313 | li $21, 8 // bytes left to transfer |
| 314 | li $22, 1 // set EP0 to TX state |
| 315 | li $23, 0 // NoData = 0 |
| 316 | |
| 317 | b _ep0_idle_state_fini |
| 318 | nop |
| 319 | |
| 320 | __ep0_set_data_address: |
| 321 | li $9, 0xffff0000 |
| 322 | and $9, $25, $9 |
| 323 | andi $8, $26, 0xffff |
| 324 | or $20, $9, $8 // data address of next transfer |
| 325 | |
| 326 | b _ep0_idle_state_fini |
| 327 | nop |
| 328 | |
| 329 | __ep0_set_data_length: |
| 330 | li $9, 0xffff0000 |
| 331 | and $9, $25, $9 |
| 332 | andi $8, $26, 0xffff |
| 333 | or $21, $9, $8 // data length of next transfer |
| 334 | |
| 335 | li $9, 0x48 // SVDOUTPKTRDY and DATAEND |
| 336 | sb $9, 0x12($27) // CSR0 |
| 337 | |
| 338 | // We must write packet to FIFO before EP1-IN interrupt here. |
| 339 | b handle_epin1_intr |
| 340 | nop |
| 341 | |
| 342 | __ep0_flush_caches: |
| 343 | // Flush dcache and invalidate icache. |
| 344 | li $8, 0x80000000 |
| 345 | addi $9, $8, 0x3fe0 // total 16KB |
| 346 | |
| 347 | 1: |
| 348 | cache 0x0, 0($8) // Index_Invalidate_I |
| 349 | cache 0x1, 0($8) // Index_Writeback_Inv_D |
| 350 | bne $8, $9, 1b |
| 351 | addiu $8, $8, 32 |
| 352 | |
| 353 | // flush write-buffer |
| 354 | sync |
| 355 | |
| 356 | // Invalidate BTB |
| 357 | mfc0 $8, $16, 7 // CP0_CONFIG |
| 358 | nop |
| 359 | ori $8, 2 |
| 360 | mtc0 $8, $16, 7 |
| 361 | nop |
| 362 | |
| 363 | b _ep0_idle_state_fini |
| 364 | nop |
| 365 | |
| 366 | __ep0_prog_start1: |
| 367 | li $9, 0x48 // SVDOUTPKTRDY and DATAEND |
| 368 | sb $9, 0x12($27) // CSR0 |
| 369 | |
| 370 | li $9, 0xffff0000 |
| 371 | and $9, $25, $9 |
| 372 | andi $8, $26, 0xffff |
| 373 | or $20, $9, $8 // target address |
| 374 | |
| 375 | b xfer_d2i |
| 376 | li $19, 0x2000 // 16KB data length |
| 377 | |
| 378 | __ep0_prog_start2: |
| 379 | li $9, 0x48 // SVDOUTPKTRDY and DATAEND |
| 380 | sb $9, 0x12($27) // CSR0 |
| 381 | |
| 382 | li $9, 0xffff0000 |
| 383 | and $9, $25, $9 |
| 384 | andi $8, $26, 0xffff |
| 385 | or $20, $9, $8 // target address |
| 386 | |
| 387 | jalr $20 // jump, and place the return address in $31 |
| 388 | nop |
| 389 | |
| 390 | __ep0_prog_start2_return: |
| 391 | // User code can return to here after executing itself, by jumping to $31. |
| 392 | b usb_boot_return |
| 393 | nop |
| 394 | |
| 395 | //-------------------------------------------------------------- |
| 396 | // 2.1.2 Standard setup request |
| 397 | //-------------------------------------------------------------- |
| 398 | _ep0_std_req: |
| 399 | andi $12, $25, 0xff00 // check bRequest |
| 400 | srl $12, $12, 8 |
| 401 | sub $9, $12, 0x05 // check USB_REQ_SET_ADDRESS |
| 402 | bnez $9, __ep0_req_set_config |
| 403 | nop |
| 404 | |
| 405 | //-------------------------------------------------------------- |
| 406 | // Handle USB_REQ_SET_ADDRESS |
| 407 | //-------------------------------------------------------------- |
| 408 | __ep0_req_set_addr: |
| 409 | srl $9, $25, 16 // get wValue |
| 410 | sb $9, 0x0($27) // set FADDR |
| 411 | li $23, 1 // NoData = 1 |
| 412 | b _ep0_idle_state_fini |
| 413 | nop |
| 414 | |
| 415 | __ep0_req_set_config: |
| 416 | sub $9, $12, 0x09 // check USB_REQ_SET_CONFIGURATION |
| 417 | bnez $9, __ep0_req_get_desc |
| 418 | nop |
| 419 | |
| 420 | //-------------------------------------------------------------- |
| 421 | // Handle USB_REQ_SET_CONFIGURATION |
| 422 | //-------------------------------------------------------------- |
| 423 | li $23, 1 // NoData = 1 |
| 424 | b _ep0_idle_state_fini |
| 425 | nop |
| 426 | |
| 427 | __ep0_req_get_desc: |
| 428 | sub $9, $12, 0x06 // check USB_REQ_GET_DESCRIPTOR |
| 429 | bnez $9, _ep0_idle_state_fini |
| 430 | li $23, 1 // NoData = 1 |
| 431 | |
| 432 | //-------------------------------------------------------------- |
| 433 | // Handle USB_REQ_GET_DESCRIPTOR |
| 434 | //-------------------------------------------------------------- |
| 435 | li $23, 0 // NoData = 0 |
| 436 | |
| 437 | srl $9, $25, 24 // wValue >> 8 |
| 438 | sub $8, $9, 0x01 // check USB_DT_DEVICE |
| 439 | beqz $8, ___ep0_get_dev_desc |
| 440 | srl $21, $26, 16 // get wLength |
| 441 | sub $8, $9, 0x02 // check USB_DT_CONFIG |
| 442 | beqz $8, ___ep0_get_conf_desc |
| 443 | sub $8, $9, 0x03 // check USB_DT_STRING |
| 444 | beqz $8, ___ep0_get_string_desc |
| 445 | sub $8, $9, 0x06 // check USB_DT_DEVICE_QUALIFIER |
| 446 | beqz $8, ___ep0_get_dev_qualifier |
| 447 | nop |
| 448 | b _ep0_idle_state_fini |
| 449 | nop |
| 450 | |
| 451 | ___ep0_get_dev_desc: |
| 452 | load_addr $20, device_desc // data pointer |
| 453 | li $22, 1 // set EP0 to TX state |
| 454 | sub $8, $21, 18 |
| 455 | blez $8, _ep0_idle_state_fini // wLength <= 18 |
| 456 | nop |
| 457 | li $21, 18 // max length of device_desc |
| 458 | b _ep0_idle_state_fini |
| 459 | nop |
| 460 | |
| 461 | ___ep0_get_dev_qualifier: |
| 462 | load_addr $20, dev_qualifier // data pointer |
| 463 | li $22, 1 // set EP0 to TX state |
| 464 | sub $8, $21, 10 |
| 465 | blez $8, _ep0_idle_state_fini // wLength <= 10 |
| 466 | nop |
| 467 | li $21, 10 // max length of dev_qualifier |
| 468 | b _ep0_idle_state_fini |
| 469 | nop |
| 470 | |
| 471 | ___ep0_get_conf_desc: |
| 472 | load_addr $20, config_desc_fs // data pointer of FS mode |
| 473 | lbu $8, 0x01($27) // read POWER |
| 474 | andi $8, 0x10 // test HS_MODE |
| 475 | beqz $8, ___ep0_get_conf_desc2 |
| 476 | nop |
| 477 | load_addr $20, config_desc_hs // data pointer of HS mode |
| 478 | |
| 479 | ___ep0_get_conf_desc2: |
| 480 | li $22, 1 // set EP0 to TX state |
| 481 | sub $8, $21, 32 |
| 482 | blez $8, _ep0_idle_state_fini // wLength <= 32 |
| 483 | nop |
| 484 | li $21, 32 // max length of config_desc |
| 485 | b _ep0_idle_state_fini |
| 486 | nop |
| 487 | |
| 488 | ___ep0_get_string_desc: |
| 489 | li $22, 1 // set EP0 to TX state |
| 490 | |
| 491 | srl $9, $25, 16 // wValue & 0xff |
| 492 | andi $9, 0xff |
| 493 | |
| 494 | sub $8, $9, 1 |
| 495 | beqz $8, ___ep0_get_string_manufacture |
| 496 | sub $8, $9, 2 |
| 497 | beqz $8, ___ep0_get_string_product |
| 498 | nop |
| 499 | |
| 500 | ___ep0_get_string_lang_ids: |
| 501 | load_addr $20, string_lang_ids // data pointer |
| 502 | b _ep0_idle_state_fini |
| 503 | li $21, 4 // data length |
| 504 | |
| 505 | ___ep0_get_string_manufacture: |
| 506 | load_addr $20, string_manufacture // data pointer |
| 507 | b _ep0_idle_state_fini |
| 508 | li $21, 16 // data length |
| 509 | |
| 510 | ___ep0_get_string_product: |
| 511 | load_addr $20, string_product // data pointer |
| 512 | b _ep0_idle_state_fini |
| 513 | li $21, 46 // data length |
| 514 | |
| 515 | _ep0_idle_state_fini: |
| 516 | li $9, 0x40 // SVDOUTPKTRDY |
| 517 | beqz $23, _ep0_idle_state_fini2 |
| 518 | nop |
| 519 | ori $9, $9, 0x08 // DATAEND |
| 520 | _ep0_idle_state_fini2: |
| 521 | sb $9, 0x12($27) // CSR0 |
| 522 | beqz $22, check_intr_ep1in |
| 523 | nop |
| 524 | |
| 525 | //-------------------------------------------------------------- |
| 526 | // 2.2 Handle EP0 TX state interrupt |
| 527 | //-------------------------------------------------------------- |
| 528 | ep0_tx_state: |
| 529 | sub $9, $22, 1 |
| 530 | bnez $9, check_intr_ep1in |
| 531 | nop |
| 532 | |
| 533 | sub $9, $21, 64 // max packetsize |
| 534 | blez $9, _ep0_tx_state2 // data count <= 64 |
| 535 | ori $19, $21, 0 |
| 536 | li $19, 64 |
| 537 | |
| 538 | _ep0_tx_state2: |
| 539 | beqz $19, _ep0_tx_state3 // send ZLP |
| 540 | ori $18, $19, 0 // record bytes to be transferred |
| 541 | sub $21, $21, $19 // decrement data count |
| 542 | |
| 543 | _ep0_fifo_write_loop: |
| 544 | lbu $9, 0($20) // read data |
| 545 | sb $9, 0x20($27) // load FIFO |
| 546 | sub $19, $19, 1 // decrement counter |
| 547 | bnez $19, _ep0_fifo_write_loop |
| 548 | addi $20, $20, 1 // increment data pointer |
| 549 | |
| 550 | sub $9, $18, 64 // max packetsize |
| 551 | beqz $9, _ep0_tx_state4 |
| 552 | nop |
| 553 | |
| 554 | _ep0_tx_state3: |
| 555 | // transferred bytes < max packetsize |
| 556 | li $9, 0x0a // set INPKTRDY and DATAEND |
| 557 | sb $9, 0x12($27) // CSR0 |
| 558 | li $22, 0 // set EP0 to IDLE state |
| 559 | b check_intr_ep1in |
| 560 | nop |
| 561 | |
| 562 | _ep0_tx_state4: |
| 563 | // transferred bytes == max packetsize |
| 564 | li $9, 0x02 // set INPKTRDY |
| 565 | sb $9, 0x12($27) // CSR0 |
| 566 | b check_intr_ep1in |
| 567 | nop |
| 568 | |
| 569 | //-------------------------------------------------------------- |
| 570 | // 3. Check and handle EP1 BULK-IN interrupt |
| 571 | //-------------------------------------------------------------- |
| 572 | check_intr_ep1in: |
| 573 | andi $9, $10, 0x2 // check EP1 IN interrupt |
| 574 | beqz $9, check_intr_ep1out |
| 575 | nop |
| 576 | |
| 577 | handle_epin1_intr: |
| 578 | li $9, 1 |
| 579 | sb $9, 0x0e($27) // set INDEX 1 |
| 580 | lbu $9, 0x12($27) // read INCSR |
| 581 | |
| 582 | andi $8, $9, 0x2 // check INCSR_FFNOTEMPT |
| 583 | bnez $8, _epin1_tx_state4 |
| 584 | nop |
| 585 | |
| 586 | _epin1_write_fifo: |
| 587 | lhu $9, 0x10($27) // get INMAXP |
| 588 | sub $8, $21, $9 |
| 589 | blez $8, _epin1_tx_state1 // bytes left <= INMAXP |
| 590 | ori $19, $21, 0 |
| 591 | ori $19, $9, 0 |
| 592 | |
| 593 | _epin1_tx_state1: |
| 594 | beqz $19, _epin1_tx_state4 // No data |
| 595 | nop |
| 596 | |
| 597 | sub $21, $21, $19 // decrement data count |
| 598 | |
| 599 | srl $5, $19, 2 // # of word |
| 600 | andi $6, $19, 0x3 // # of byte |
| 601 | beqz $5, _epin1_tx_state2 |
| 602 | nop |
| 603 | |
| 604 | _epin1_fifo_write_word: |
| 605 | lw $9, 0($20) // read data from source address |
| 606 | sw $9, 0x24($27) // write FIFO |
| 607 | sub $5, $5, 1 // decrement counter |
| 608 | bnez $5, _epin1_fifo_write_word |
| 609 | addiu $20, $20, 4 // increment dest address |
| 610 | |
| 611 | _epin1_tx_state2: |
| 612 | beqz $6, _epin1_tx_state3 |
| 613 | nop |
| 614 | |
| 615 | _epin1_fifo_write_byte: |
| 616 | lbu $9, 0($20) // read data from source address |
| 617 | sb $9, 0x24($27) // write FIFO |
| 618 | sub $6, $6, 1 // decrement counter |
| 619 | bnez $6, _epin1_fifo_write_byte |
| 620 | addiu $20, $20, 1 // increment dest address |
| 621 | |
| 622 | _epin1_tx_state3: |
| 623 | li $9, 0x1 |
| 624 | sb $9, 0x12($27) // INCSR, set INPKTRDY |
| 625 | |
| 626 | _epin1_tx_state4: |
| 627 | // nop |
| 628 | |
| 629 | //-------------------------------------------------------------- |
| 630 | // 4. Check and handle EP1 BULK-OUT interrupt |
| 631 | //-------------------------------------------------------------- |
| 632 | check_intr_ep1out: |
| 633 | lhu $9, 0x04($27) // read INTROUT |
| 634 | andi $9, 0x2 |
| 635 | beqz $9, check_status_next |
| 636 | nop |
| 637 | |
| 638 | handle_epout1_intr: |
| 639 | li $9, 1 |
| 640 | sb $9, 0x0e($27) // set INDEX 1 |
| 641 | |
| 642 | lbu $9, 0x16($27) // read OUTCSR |
| 643 | andi $9, 0x1 // check OUTPKTRDY |
| 644 | beqz $9, check_status_next |
| 645 | nop |
| 646 | |
| 647 | _epout1_read_fifo: |
| 648 | lhu $19, 0x18($27) // read OUTCOUNT |
| 649 | srl $5, $19, 2 // # of word |
| 650 | andi $6, $19, 0x3 // # of byte |
| 651 | beqz $5, _epout1_rx_state1 |
| 652 | nop |
| 653 | |
| 654 | _epout1_fifo_read_word: |
| 655 | lw $9, 0x24($27) // read FIFO |
| 656 | sw $9, 0($20) // store to dest address |
| 657 | sub $5, $5, 1 // decrement counter |
| 658 | bnez $5, _epout1_fifo_read_word |
| 659 | addiu $20, $20, 4 // increment dest address |
| 660 | |
| 661 | _epout1_rx_state1: |
| 662 | beqz $6, _epout1_rx_state2 |
| 663 | nop |
| 664 | |
| 665 | _epout1_fifo_read_byte: |
| 666 | lbu $9, 0x24($27) // read FIFO |
| 667 | sb $9, 0($20) // store to dest address |
| 668 | sub $6, $6, 1 // decrement counter |
| 669 | bnez $6, _epout1_fifo_read_byte |
| 670 | addiu $20, $20, 1 // increment dest address |
| 671 | |
| 672 | _epout1_rx_state2: |
| 673 | sb $0, 0x16($27) // clear OUTPKTRDY |
| 674 | |
| 675 | check_status_next: |
| 676 | b usb_command_loop |
| 677 | nop |
| 678 | |
| 679 | //-------------------------------------------------------------- |
| 680 | // Device/Configuration/Interface/Endpoint/String Descriptors |
| 681 | //-------------------------------------------------------------- |
| 682 | |
| 683 | .align 2 |
| 684 | device_desc: |
| 685 | .byte 0x12 // bLength |
| 686 | .byte 0x01 // bDescriptorType |
| 687 | .byte 0x00 // bcdUSB |
| 688 | .byte 0x02 // bcdUSB |
| 689 | .byte 0x00 // bDeviceClass |
| 690 | .byte 0x00 // bDeviceSubClass |
| 691 | .byte 0x00 // bDeviceProtocol |
| 692 | .byte 0x40 // bMaxPacketSize0 |
| 693 | .byte 0x1a // idVendor |
| 694 | .byte 0x60 // idVendor |
| 695 | .byte 0x40 // idProduct |
| 696 | .byte 0x47 // idProduct |
| 697 | .byte 0x00 // bcdDevice |
| 698 | .byte 0x01 // bcdDevice |
| 699 | .byte 0x01 // iManufacturer |
| 700 | .byte 0x02 // iProduct |
| 701 | .byte 0x00 // iSerialNumber |
| 702 | .byte 0x01 // bNumConfigurations |
| 703 | |
| 704 | .align 2 |
| 705 | dev_qualifier: |
| 706 | .byte 0x0a // bLength |
| 707 | .byte 0x06 // bDescriptorType |
| 708 | .byte 0x00 // bcdUSB |
| 709 | .byte 0x02 // bcdUSB |
| 710 | .byte 0x00 // bDeviceClass |
| 711 | .byte 0x00 // bDeviceSubClass |
| 712 | .byte 0x00 // bDeviceProtocol |
| 713 | .byte 0x40 // bMaxPacketSize0 |
| 714 | .byte 0x01 // bNumConfigurations |
| 715 | .byte 0x00 // bRESERVED |
| 716 | |
| 717 | .align 2 |
| 718 | config_desc_hs: |
| 719 | .byte 0x09 // bLength |
| 720 | .byte 0x02 // bDescriptorType |
| 721 | .byte 0x20 // wTotalLength |
| 722 | .byte 0x00 // wTotalLength |
| 723 | .byte 0x01 // bNumInterfaces |
| 724 | .byte 0x01 // bConfigurationValue |
| 725 | .byte 0x00 // iConfiguration |
| 726 | .byte 0xc0 // bmAttributes |
| 727 | .byte 0x01 // MaxPower |
| 728 | intf_desc_hs: |
| 729 | .byte 0x09 // bLength |
| 730 | .byte 0x04 // bDescriptorType |
| 731 | .byte 0x00 // bInterfaceNumber |
| 732 | .byte 0x00 // bAlternateSetting |
| 733 | .byte 0x02 // bNumEndpoints |
| 734 | .byte 0xff // bInterfaceClass |
| 735 | .byte 0x00 // bInterfaceSubClass |
| 736 | .byte 0x50 // bInterfaceProtocol |
| 737 | .byte 0x00 // iInterface |
| 738 | ep1_desc_hs: |
| 739 | .byte 0x07 // bLength |
| 740 | .byte 0x05 // bDescriptorType |
| 741 | .byte 0x01 // bEndpointAddress |
| 742 | .byte 0x02 // bmAttributes |
| 743 | .byte 0x00 // wMaxPacketSize |
| 744 | .byte 0x02 // wMaxPacketSize |
| 745 | .byte 0x00 // bInterval |
| 746 | ep2_desc_hs: |
| 747 | .byte 0x07 // bLength |
| 748 | .byte 0x05 // bDescriptorType |
| 749 | .byte 0x81 // bEndpointAddress |
| 750 | .byte 0x02 // bmAttributes |
| 751 | .byte 0x00 // wMaxPacketSize |
| 752 | .byte 0x02 // wMaxPacketSize |
| 753 | .byte 0x00 // bInterval |
| 754 | |
| 755 | .align 2 |
| 756 | config_desc_fs: |
| 757 | .byte 0x09 // bLength |
| 758 | .byte 0x02 // bDescriptorType |
| 759 | .byte 0x20 // wTotalLength |
| 760 | .byte 0x00 // wTotalLength |
| 761 | .byte 0x01 // bNumInterfaces |
| 762 | .byte 0x01 // bConfigurationValue |
| 763 | .byte 0x00 // iConfiguration |
| 764 | .byte 0xc0 // bmAttributes |
| 765 | .byte 0x01 // MaxPower |
| 766 | intf_desc_fs: |
| 767 | .byte 0x09 // bLength |
| 768 | .byte 0x04 // bDescriptorType |
| 769 | .byte 0x00 // bInterfaceNumber |
| 770 | .byte 0x00 // bAlternateSetting |
| 771 | .byte 0x02 // bNumEndpoints |
| 772 | .byte 0xff // bInterfaceClass |
| 773 | .byte 0x00 // bInterfaceSubClass |
| 774 | .byte 0x50 // bInterfaceProtocol |
| 775 | .byte 0x00 // iInterface |
| 776 | ep1_desc_fs: |
| 777 | .byte 0x07 // bLength |
| 778 | .byte 0x05 // bDescriptorType |
| 779 | .byte 0x01 // bEndpointAddress |
| 780 | .byte 0x02 // bmAttributes |
| 781 | .byte 0x40 // wMaxPacketSize |
| 782 | .byte 0x00 // wMaxPacketSize |
| 783 | .byte 0x00 // bInterval |
| 784 | ep2_desc_fs: |
| 785 | .byte 0x07 // bLength |
| 786 | .byte 0x05 // bDescriptorType |
| 787 | .byte 0x81 // bEndpointAddress |
| 788 | .byte 0x02 // bmAttributes |
| 789 | .byte 0x40 // wMaxPacketSize |
| 790 | .byte 0x00 // wMaxPacketSize |
| 791 | .byte 0x00 // bInterval |
| 792 | |
| 793 | .align 2 |
| 794 | string_lang_ids: |
| 795 | .byte 0x04 |
| 796 | .byte 0x03 |
| 797 | .byte 0x09 |
| 798 | .byte 0x04 |
| 799 | |
| 800 | .align 2 |
| 801 | string_manufacture: |
| 802 | .byte 0x10 |
| 803 | .byte 0x03 |
| 804 | .byte 0x49 |
| 805 | .byte 0x00 |
| 806 | .byte 0x6e |
| 807 | .byte 0x00 |
| 808 | .byte 0x67 |
| 809 | .byte 0x00 |
| 810 | .byte 0x65 |
| 811 | .byte 0x00 |
| 812 | .byte 0x6e |
| 813 | .byte 0x00 |
| 814 | .byte 0x69 |
| 815 | .byte 0x00 |
| 816 | .byte 0x63 |
| 817 | .byte 0x00 |
| 818 | |
| 819 | .align 2 |
| 820 | string_product: |
| 821 | .byte 0x2e |
| 822 | .byte 0x03 |
| 823 | .byte 0x4a |
| 824 | .byte 0x00 |
| 825 | .byte 0x5a |
| 826 | .byte 0x00 |
| 827 | .byte 0x34 |
| 828 | .byte 0x00 |
| 829 | .byte 0x37 |
| 830 | .byte 0x00 |
| 831 | .byte 0x34 |
| 832 | .byte 0x00 |
| 833 | .byte 0x30 |
| 834 | .byte 0x00 |
| 835 | .byte 0x20 |
| 836 | .byte 0x00 |
| 837 | .byte 0x55 |
| 838 | .byte 0x00 |
| 839 | .byte 0x53 |
| 840 | .byte 0x00 |
| 841 | .byte 0x42 |
| 842 | .byte 0x00 |
| 843 | .byte 0x20 |
| 844 | .byte 0x00 |
| 845 | .byte 0x42 |
| 846 | .byte 0x00 |
| 847 | .byte 0x6f |
| 848 | .byte 0x00 |
| 849 | .byte 0x6f |
| 850 | .byte 0x00 |
| 851 | .byte 0x74 |
| 852 | .byte 0x00 |
| 853 | .byte 0x20 |
| 854 | .byte 0x00 |
| 855 | .byte 0x44 |
| 856 | .byte 0x00 |
| 857 | .byte 0x65 |
| 858 | .byte 0x00 |
| 859 | .byte 0x76 |
| 860 | .byte 0x00 |
| 861 | .byte 0x69 |
| 862 | .byte 0x00 |
| 863 | .byte 0x63 |
| 864 | .byte 0x00 |
| 865 | .byte 0x65 |
| 866 | .byte 0x00 |
| 867 | |
| 868 | .align 2 |
| 869 | cpu_info_data: |
| 870 | .byte 0x4a |
| 871 | .byte 0x5a |
| 872 | .byte 0x34 |
| 873 | .byte 0x37 |
| 874 | .byte 0x34 |
| 875 | .byte 0x30 |
| 876 | .byte 0x56 |
| 877 | .byte 0x31 |
| 878 | usbboot_end: |
| 879 | |
| 880 | .set reorder |
| 881 | |
