Root/package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.c

1/*
2 * JzRISC lcd controller
3 *
4 * Xiangfu Liu <xiangfu@sharism.cc>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include <config.h>
23#include <common.h>
24#include <lcd.h>
25
26#include <asm/io.h> /* virt_to_phys() */
27
28#include <asm/jz4740.h>
29#include "nanonote_gpm940b0.h"
30
31#define align2(n) (n)=((((n)+1)>>1)<<1)
32#define align4(n) (n)=((((n)+3)>>2)<<2)
33#define align8(n) (n)=((((n)+7)>>3)<<3)
34
35struct jzfb_info {
36    unsigned int cfg; /* panel mode and pin usage etc. */
37    unsigned int w;
38    unsigned int h;
39    unsigned int bpp; /* bit per pixel */
40    unsigned int fclk; /* frame clk */
41    unsigned int hsw; /* hsync width, in pclk */
42    unsigned int vsw; /* vsync width, in line count */
43    unsigned int elw; /* end of line, in pclk */
44    unsigned int blw; /* begin of line, in pclk */
45    unsigned int efw; /* end of frame, in line count */
46    unsigned int bfw; /* begin of frame, in line count */
47};
48
49static struct jzfb_info jzfb = {
50    MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
51    320, 240, 32, 70, 1, 1, 273, 140, 1, 20
52};
53
54vidinfo_t panel_info = {
55    320, 240, LCD_BPP,
56};
57
58int lcd_line_length;
59int lcd_color_fg;
60int lcd_color_bg;
61/*
62 * Frame buffer memory information
63 */
64void *lcd_base; /* Start of framebuffer memory */
65void *lcd_console_address; /* Start of console buffer */
66
67short console_col;
68short console_row;
69
70void lcd_ctrl_init (void *lcdbase);
71void lcd_enable (void);
72void lcd_disable (void);
73
74static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
75static void jz_lcd_desc_init(vidinfo_t *vid);
76static int jz_lcd_hw_init(vidinfo_t *vid);
77extern int flush_cache_all(void);
78
79void lcd_ctrl_init (void *lcdbase)
80{
81    jz_lcd_init_mem(lcdbase, &panel_info);
82    jz_lcd_desc_init(&panel_info);
83    jz_lcd_hw_init(&panel_info);
84}
85
86/*
87 * Before enabled lcd controller, lcd registers should be configured correctly.
88 */
89void lcd_enable (void)
90{
91    REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
92    REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
93}
94
95void lcd_disable (void)
96{
97    REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
98    /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */
99}
100
101static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
102{
103    u_long palette_mem_size;
104    struct jz_fb_info *fbi = &vid->jz_fb;
105    int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
106
107    fbi->screen = (u_long)lcdbase;
108    fbi->palette_size = 256;
109    palette_mem_size = fbi->palette_size * sizeof(u16);
110
111    debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
112    /* locate palette and descs at end of page following fb */
113    fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
114
115    return 0;
116}
117
118static void jz_lcd_desc_init(vidinfo_t *vid)
119{
120    struct jz_fb_info * fbi;
121    fbi = &vid->jz_fb;
122    fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
123    fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
124    fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
125
126    #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
127
128    /* populate descriptors */
129    fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
130    fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
131    fbi->dmadesc_fblow->fidr = 0;
132    fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
133
134    fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
135
136    fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
137    fbi->dmadesc_fbhigh->fidr = 0;
138    fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
139
140    fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
141    fbi->dmadesc_palette->fidr = 0;
142    fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
143
144    if(NBITS(vid->vl_bpix) < 12)
145    {
146        /* assume any mode with <12 bpp is palette driven */
147        fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
148        fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
149        /* flips back and forth between pal and fbhigh */
150        fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
151    } else {
152        /* palette shouldn't be loaded in true-color mode */
153        fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
154        fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
155    }
156
157    flush_cache_all();
158}
159
160static int jz_lcd_hw_init(vidinfo_t *vid)
161{
162    struct jz_fb_info *fbi = &vid->jz_fb;
163    unsigned int val = 0;
164    unsigned int pclk;
165    unsigned int stnH;
166    int pll_div;
167
168    /* Setting Control register */
169    switch (jzfb.bpp) {
170    case 1:
171        val |= LCD_CTRL_BPP_1;
172        break;
173    case 2:
174        val |= LCD_CTRL_BPP_2;
175        break;
176    case 4:
177        val |= LCD_CTRL_BPP_4;
178        break;
179    case 8:
180        val |= LCD_CTRL_BPP_8;
181        break;
182    case 15:
183        val |= LCD_CTRL_RGB555;
184    case 16:
185        val |= LCD_CTRL_BPP_16;
186        break;
187    case 17 ... 32:
188        val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
189        break;
190
191    default:
192        printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
193        val |= LCD_CTRL_BPP_16;
194        break;
195    }
196
197    switch (jzfb.cfg & MODE_MASK) {
198    case MODE_STN_MONO_DUAL:
199    case MODE_STN_COLOR_DUAL:
200    case MODE_STN_MONO_SINGLE:
201    case MODE_STN_COLOR_SINGLE:
202        switch (jzfb.bpp) {
203        case 1:
204            /* val |= LCD_CTRL_PEDN; */
205        case 2:
206            val |= LCD_CTRL_FRC_2;
207            break;
208        case 4:
209            val |= LCD_CTRL_FRC_4;
210            break;
211        case 8:
212        default:
213            val |= LCD_CTRL_FRC_16;
214            break;
215        }
216        break;
217    }
218
219    val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
220    val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
221
222    switch (jzfb.cfg & MODE_MASK) {
223    case MODE_STN_MONO_DUAL:
224    case MODE_STN_COLOR_DUAL:
225    case MODE_STN_MONO_SINGLE:
226    case MODE_STN_COLOR_SINGLE:
227        switch (jzfb.cfg & STN_DAT_PINMASK) {
228        case STN_DAT_PIN1:
229            /* Do not adjust the hori-param value. */
230            break;
231        case STN_DAT_PIN2:
232            align2(jzfb.hsw);
233            align2(jzfb.elw);
234            align2(jzfb.blw);
235            break;
236        case STN_DAT_PIN4:
237            align4(jzfb.hsw);
238            align4(jzfb.elw);
239            align4(jzfb.blw);
240            break;
241        case STN_DAT_PIN8:
242            align8(jzfb.hsw);
243            align8(jzfb.elw);
244            align8(jzfb.blw);
245            break;
246        }
247        break;
248    }
249
250    REG_LCD_CTRL = val;
251
252    switch (jzfb.cfg & MODE_MASK) {
253    case MODE_STN_MONO_DUAL:
254    case MODE_STN_COLOR_DUAL:
255    case MODE_STN_MONO_SINGLE:
256    case MODE_STN_COLOR_SINGLE:
257        if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
258            ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
259            stnH = jzfb.h >> 1;
260        else
261            stnH = jzfb.h;
262
263        REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
264        REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
265
266        /* Screen setting */
267        REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
268        REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
269        REG_LCD_DAV = (0 << 16) | (stnH);
270
271        /* AC BIAs signal */
272        REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
273
274        break;
275
276    case MODE_TFT_GEN:
277    case MODE_TFT_SHARP:
278    case MODE_TFT_CASIO:
279    case MODE_TFT_SAMSUNG:
280    case MODE_8BIT_SERIAL_TFT:
281    case MODE_TFT_18BIT:
282        REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
283        REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
284        REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
285        REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
286        REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
287            | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
288        break;
289    }
290
291    switch (jzfb.cfg & MODE_MASK) {
292    case MODE_TFT_SAMSUNG:
293    {
294        unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
295        unsigned int rev_s, rev_e, inv_s, inv_e;
296
297        pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
298            (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
299
300        total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
301        tp_s = jzfb.blw + jzfb.w + 1;
302        tp_e = tp_s + 1;
303        /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
304        ckv_s = tp_s - pclk/(1000000000/4100);
305        ckv_e = tp_s + total;
306        rev_s = tp_s - 11; /* -11.5 clk */
307        rev_e = rev_s + total;
308        inv_s = tp_s;
309        inv_e = inv_s + total;
310        REG_LCD_CLS = (tp_s << 16) | tp_e;
311        REG_LCD_PS = (ckv_s << 16) | ckv_e;
312        REG_LCD_SPL = (rev_s << 16) | rev_e;
313        REG_LCD_REV = (inv_s << 16) | inv_e;
314        jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
315        break;
316    }
317    case MODE_TFT_SHARP:
318    {
319        unsigned int total, cls_s, cls_e, ps_s, ps_e;
320        unsigned int spl_s, spl_e, rev_s, rev_e;
321        total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
322        spl_s = 1;
323        spl_e = spl_s + 1;
324        cls_s = 0;
325        cls_e = total - 60; /* > 4us (pclk = 80ns) */
326        ps_s = cls_s;
327        ps_e = cls_e;
328        rev_s = total - 40; /* > 3us (pclk = 80ns) */
329        rev_e = rev_s + total;
330        jzfb.cfg |= STFT_PSHI;
331        REG_LCD_SPL = (spl_s << 16) | spl_e;
332        REG_LCD_CLS = (cls_s << 16) | cls_e;
333        REG_LCD_PS = (ps_s << 16) | ps_e;
334        REG_LCD_REV = (rev_s << 16) | rev_e;
335        break;
336    }
337    case MODE_TFT_CASIO:
338        break;
339    }
340
341    /* Configure the LCD panel */
342    REG_LCD_CFG = jzfb.cfg;
343
344    /* Timing setting */
345    __cpm_stop_lcd();
346
347    val = jzfb.fclk; /* frame clk */
348    if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
349        pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
350            (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
351    } else {
352        /* serial mode: Hsync period = 3*Width_Pixel */
353        pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
354            (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
355    }
356
357    if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
358        ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
359        pclk = (pclk * 3);
360
361    if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
362        ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
363        ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
364        ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
365        pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
366
367    if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
368        ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
369        pclk >>= 1;
370
371    pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
372    pll_div = pll_div ? 1 : 2 ;
373    val = ( __cpm_get_pllout()/pll_div ) / pclk;
374    val--;
375    if ( val > 0x1ff ) {
376        printf("CPM_LPCDR too large, set it to 0x1ff\n");
377        val = 0x1ff;
378    }
379    __cpm_set_pixdiv(val);
380
381    val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
382    if ( val > 150000000 ) {
383        printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
384        printf("Change LCDClock to 150MHz\n");
385        val = 150000000;
386    }
387    val = ( __cpm_get_pllout()/pll_div ) / val;
388    val--;
389    if ( val > 0x1f ) {
390        printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
391        val = 0x1f;
392    }
393    __cpm_set_ldiv( val );
394    REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
395
396    __cpm_start_lcd();
397    udelay(1000);
398
399    REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
400
401    if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
402        ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
403        REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
404
405    return 0;
406}
407
408void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
409{
410}
411
412void lcd_initcolregs (void)
413{
414}
415

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