| 1 | /* |
| 2 | * Authors: Xiangfu Liu <xiangfu.z@gmail.com> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation; either version |
| 7 | * 3 of the License, or (at your option) any later version. |
| 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * This file contains the configuration parameters for SAKC. |
| 12 | */ |
| 13 | #ifndef __CONFIG_H |
| 14 | #define __CONFIG_H |
| 15 | |
| 16 | #define DEBUG |
| 17 | #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ |
| 18 | #define CONFIG_JzRISC 1 /* JzRISC core */ |
| 19 | #define CONFIG_JZSOC 1 /* Jz SoC */ |
| 20 | #define CONFIG_JZ4740 1 /* Jz4740 SoC */ |
| 21 | #define CONFIG_SAKC 1 /* SAKC board */ |
| 22 | #define CONFIG_NANONOTE |
| 23 | #define CONFIG_NAND_JZ4740 |
| 24 | |
| 25 | #define BOOT_FROM_SDCARD 1 |
| 26 | #define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */ |
| 27 | |
| 28 | #define MMC_BUS_WIDTH_1BIT 1 /* 1 for MMC 1Bit Bus Width */ |
| 29 | |
| 30 | //#define CONFIG_LCD 1 /* LCD support */ |
| 31 | //#define LCD_BPP LCD_COLOR32 /*5:18,24,32 bits per pixel */ |
| 32 | //#define CONFIG_SYS_WHITE_ON_BLACK 1 |
| 33 | |
| 34 | #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ |
| 35 | #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ |
| 36 | #define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */ |
| 37 | #define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED |
| 38 | |
| 39 | #define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */ |
| 40 | #define CONFIG_BAUDRATE 57600 |
| 41 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 42 | |
| 43 | #define CONFIG_MMC 1 |
| 44 | #define CONFIG_FAT 1 |
| 45 | #define CONFIG_DOS_PARTITION 1 |
| 46 | #define CONFIG_SKIP_LOWLEVEL_INIT 1 |
| 47 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
| 48 | #define CONFIG_SYS_NO_FLASH 1 |
| 49 | #define CONFIG_ENV_OVERWRITE 1 |
| 50 | |
| 51 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL) |
| 52 | #define CONFIG_BOOTDELAY 3 |
| 53 | #define CONFIG_BOOTFILE "uImage" /* file to load */ |
| 54 | #define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" |
| 55 | |
| 56 | #define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait" |
| 57 | #define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" |
| 58 | |
| 59 | /* |
| 60 | * Command line configuration. |
| 61 | */ |
| 62 | #define CONFIG_CMD_BDI /* bdinfo */ |
| 63 | #define CONFIG_CMD_BOOTD /* bootd */ |
| 64 | #define CONFIG_CMD_CONSOLE /* coninfo */ |
| 65 | #define CONFIG_CMD_ECHO /* echo arguments */ |
| 66 | #define CONFIG_CMD_IMI /* iminfo */ |
| 67 | #define CONFIG_CMD_ITEST /* Integer (and string) test */ |
| 68 | |
| 69 | #define CONFIG_CMD_LOADB /* loadb */ |
| 70 | #define CONFIG_CMD_LOADS /* loads */ |
| 71 | #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ |
| 72 | #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ |
| 73 | #define CONFIG_CMD_RUN /* run command in env variable */ |
| 74 | #define CONFIG_CMD_SAVEENV /* saveenv */ |
| 75 | #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ |
| 76 | #define CONFIG_CMD_SOURCE /* "source" command support */ |
| 77 | #define CONFIG_CMD_XIMG /* Load part of Multi Image */ |
| 78 | |
| 79 | #define CONFIG_CMD_NAND |
| 80 | #define CONFIG_CMD_MMC |
| 81 | #define CONFIG_CMD_FAT |
| 82 | |
| 83 | /* |
| 84 | * Serial download configuration |
| 85 | */ |
| 86 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 87 | #define CONFIG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 88 | |
| 89 | /* |
| 90 | * Miscellaneous configurable options |
| 91 | */ |
| 92 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 93 | #define CONFIG_SYS_PROMPT "SAKC# " /* Monitor Command Prompt */ |
| 94 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 95 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 96 | /* Print Buffer Size */ |
| 97 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ |
| 98 | |
| 99 | #define CONFIG_SYS_MALLOC_LEN 128 * 1024 |
| 100 | #define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024 |
| 101 | |
| 102 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ |
| 103 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
| 104 | #define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */ |
| 105 | #define CONFIG_SYS_MEMTEST_START 0x80100000 |
| 106 | #define CONFIG_SYS_MEMTEST_END 0x80800000 |
| 107 | |
| 108 | /* |
| 109 | * Environment |
| 110 | */ |
| 111 | #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ |
| 112 | |
| 113 | /* |
| 114 | * NAND FLASH configuration |
| 115 | */ |
| 116 | /* NAND Boot config code */ |
| 117 | #define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 |
| 118 | |
| 119 | #define SAKC_NAND_SIZE 1 /* if board nand flash is 1GB, set to 1 |
| 120 | * if board nand flash is 2GB, set to 2 |
| 121 | * for change the PAGE_SIZE and BLOCK_SIZE |
| 122 | * will delete when there is no 1GB flash |
| 123 | */ |
| 124 | |
| 125 | #define CONFIG_SYS_NAND_PAGE_SIZE (2048 * SAKC_NAND_SIZE) |
| 126 | /* nand chip block size */ |
| 127 | #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * SAKC_NAND_SIZE << 10) |
| 128 | /* nand bad block was marked at this page in a block, start from 0 */ |
| 129 | #define CONFIG_SYS_NAND_BADBLOCK_PAGE 127 |
| 130 | /* ECC offset position in oob area, default value is 6 if it isn't defined */ |
| 131 | #define CONFIG_SYS_NAND_ECC_POS (6 * SAKC_NAND_SIZE) |
| 132 | #define CONFIG_SYS_NAND_ECCSIZE 512 |
| 133 | #define CONFIG_SYS_NAND_ECCBYTES 9 |
| 134 | |
| 135 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 136 | #define NAND_MAX_CHIPS 1 |
| 137 | #define CONFIG_SYS_NAND_BASE 0xB8000000 |
| 138 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/ |
| 139 | #define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE |
| 140 | |
| 141 | /* |
| 142 | * IPL (Initial Program Loader, integrated inside CPU) |
| 143 | * Will load first 8k from NAND (SPL) into cache and execute it from there. |
| 144 | * |
| 145 | * SPL (Secondary Program Loader) |
| 146 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL |
| 147 | * has to fit into 8kByte. It sets up the CPU and configures the SDRAM |
| 148 | * controller and the NAND controller so that the special U-Boot image can be |
| 149 | * loaded from NAND to SDRAM. |
| 150 | * |
| 151 | * NUB (NAND U-Boot) |
| 152 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started |
| 153 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. |
| 154 | * |
| 155 | */ |
| 156 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */ |
| 157 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST |
| 158 | /* Start NUB from this addr*/ |
| 159 | |
| 160 | /* |
| 161 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) |
| 162 | */ |
| 163 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */ |
| 164 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ |
| 165 | |
| 166 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| 167 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE) |
| 168 | /* environment starts here */ |
| 169 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
| 170 | |
| 171 | /* in qi_lb60.h/config.mk TEXT_BAS = 0x88000000 */ |
| 172 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
| 173 | |
| 174 | /* |
| 175 | * SDRAM Info. |
| 176 | */ |
| 177 | #define CONFIG_NR_DRAM_BANKS 1 |
| 178 | |
| 179 | /* SDRAM paramters */ |
| 180 | #define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ |
| 181 | #define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ |
| 182 | #define SDRAM_ROW 13 /* Row address: 11 to 13 */ |
| 183 | #define SDRAM_COL 9 /* Column address: 8 to 12 */ |
| 184 | #define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ |
| 185 | |
| 186 | /* SDRAM Timings, unit: ns */ |
| 187 | #define SDRAM_TRAS 45 /* RAS# Active Time */ |
| 188 | #define SDRAM_RCD 20 /* RAS# to CAS# Delay */ |
| 189 | #define SDRAM_TPC 20 /* RAS# Precharge Time */ |
| 190 | #define SDRAM_TRWL 7 /* Write Latency Time */ |
| 191 | #define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ |
| 192 | |
| 193 | /* |
| 194 | * Cache Configuration |
| 195 | */ |
| 196 | #define CONFIG_SYS_DCACHE_SIZE 16384 |
| 197 | #define CONFIG_SYS_ICACHE_SIZE 16384 |
| 198 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
| 199 | |
| 200 | /* |
| 201 | * GPIO definition |
| 202 | */ |
| 203 | #define GPIO_SD_DETECT (2 * 32 + 27) |
| 204 | #define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */ |
| 205 | #define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */ |
| 206 | |
| 207 | #endif /* __CONFIG_H */ |
| 208 | |
