Root/package/ubsec_ssb/src/ubsecvar.h

1
2/*
3 * Copyright (c) 2008 Daniel Mueller (daniel@danm.de)
4 * Copyright (c) 2000 Theo de Raadt
5 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Effort sponsored in part by the Defense Advanced Research Projects
29 * Agency (DARPA) and Air Force Research Laboratory, Air Force
30 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
31 *
32 */
33
34/* Maximum queue length */
35#ifndef UBS_MAX_NQUEUE
36#define UBS_MAX_NQUEUE 60
37#endif
38
39#define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */
40
41#ifndef UBS_MAX_AGGR
42#define UBS_MAX_AGGR 5 /* Maximum aggregation count */
43#endif
44
45#define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28)
46#define UBSEC_SESSION(sid) ( (sid) & 0x0fffffff)
47#define UBSEC_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff))
48
49#define UBS_DEF_RTY 0xff /* PCI Retry Timeout */
50#define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */
51#define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */
52
53#define DEFAULT_HMAC_LEN 12
54
55struct ubsec_dma_alloc {
56    dma_addr_t dma_paddr;
57    void *dma_vaddr;
58    /*
59    bus_dmamap_t dma_map;
60    bus_dma_segment_t dma_seg;
61    */
62    size_t dma_size;
63    /*
64    int dma_nseg;
65    */
66};
67
68struct ubsec_q2 {
69    BSD_SIMPLEQ_ENTRY(ubsec_q2) q_next;
70    struct ubsec_dma_alloc q_mcr;
71    struct ubsec_dma_alloc q_ctx;
72    u_int q_type;
73};
74
75struct ubsec_q2_rng {
76    struct ubsec_q2 rng_q;
77    struct ubsec_dma_alloc rng_buf;
78    int rng_used;
79};
80
81/* C = (M ^ E) mod N */
82#define UBS_MODEXP_PAR_M 0
83#define UBS_MODEXP_PAR_E 1
84#define UBS_MODEXP_PAR_N 2
85struct ubsec_q2_modexp {
86    struct ubsec_q2 me_q;
87    struct cryptkop * me_krp;
88    struct ubsec_dma_alloc me_M;
89    struct ubsec_dma_alloc me_E;
90    struct ubsec_dma_alloc me_C;
91    struct ubsec_dma_alloc me_epb;
92    int me_modbits;
93    int me_shiftbits;
94    int me_normbits;
95};
96
97#define UBS_RSAPRIV_PAR_P 0
98#define UBS_RSAPRIV_PAR_Q 1
99#define UBS_RSAPRIV_PAR_DP 2
100#define UBS_RSAPRIV_PAR_DQ 3
101#define UBS_RSAPRIV_PAR_PINV 4
102#define UBS_RSAPRIV_PAR_MSGIN 5
103#define UBS_RSAPRIV_PAR_MSGOUT 6
104struct ubsec_q2_rsapriv {
105    struct ubsec_q2 rpr_q;
106    struct cryptkop * rpr_krp;
107    struct ubsec_dma_alloc rpr_msgin;
108    struct ubsec_dma_alloc rpr_msgout;
109};
110
111#define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */
112
113struct ubsec_dmachunk {
114    struct ubsec_mcr d_mcr;
115    struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1];
116    struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1];
117    struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1];
118    u_int32_t d_macbuf[5];
119    union {
120        struct ubsec_pktctx_aes256 ctxaes256;
121        struct ubsec_pktctx_aes192 ctxaes192;
122        struct ubsec_pktctx_des ctxdes;
123        struct ubsec_pktctx_aes128 ctxaes128;
124        struct ubsec_pktctx ctx;
125    } d_ctx;
126};
127
128struct ubsec_dma {
129    BSD_SIMPLEQ_ENTRY(ubsec_dma) d_next;
130    struct ubsec_dmachunk *d_dma;
131    struct ubsec_dma_alloc d_alloc;
132};
133
134#define UBS_FLAGS_KEY 0x01 /* has key accelerator */
135#define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */
136#define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */
137#define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */
138#define UBS_FLAGS_RNG 0x10 /* hardware rng */
139#define UBS_FLAGS_AES 0x20 /* hardware AES support */
140
141struct ubsec_q {
142    BSD_SIMPLEQ_ENTRY(ubsec_q) q_next;
143    int q_nstacked_mcrs;
144    struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1];
145    struct cryptop *q_crp;
146    struct ubsec_dma *q_dma;
147
148    //struct mbuf *q_src_m, *q_dst_m;
149    struct sk_buff *q_src_m, *q_dst_m;
150    struct uio *q_src_io, *q_dst_io;
151
152    /*
153    bus_dmamap_t q_src_map;
154    bus_dmamap_t q_dst_map;
155    */
156
157    /* DMA addresses for In-/Out packages */
158    int q_src_len;
159    int q_dst_len;
160    struct ubsec_dma_alloc q_src_map[UBS_MAX_SCATTER];
161    struct ubsec_dma_alloc q_dst_map[UBS_MAX_SCATTER];
162    int q_has_dst;
163
164    int q_sesn;
165    int q_flags;
166};
167
168struct ubsec_softc {
169    softc_device_decl sc_dev;
170    struct ssb_device *sdev; /* device backpointer */
171
172    struct device *sc_dv; /* generic device */
173    void *sc_ih; /* interrupt handler cookie */
174    int sc_flags; /* device specific flags */
175    u_int32_t sc_statmask; /* interrupt status mask */
176    int32_t sc_cid; /* crypto tag */
177    BSD_SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */
178    int sc_nqueue; /* count enqueued, mcr1 */
179    BSD_SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */
180    BSD_SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */
181    BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */
182    int sc_nqueue2; /* count enqueued, mcr2 */
183    BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */
184    int sc_nsessions; /* # of sessions */
185    struct ubsec_session *sc_sessions; /* sessions */
186    int sc_rnghz; /* rng poll time */
187    struct ubsec_q2_rng sc_rng;
188    struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE];
189    struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE];
190    BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */
191    spinlock_t sc_ringmtx; /* PE ring lock */
192};
193
194#define UBSEC_QFLAGS_COPYOUTIV 0x1
195
196struct ubsec_session {
197    u_int32_t ses_used;
198    u_int32_t ses_key[8]; /* 3DES/AES key */
199    u_int32_t ses_hminner[5]; /* hmac inner state */
200    u_int32_t ses_hmouter[5]; /* hmac outer state */
201    u_int32_t ses_iv[4]; /* [3]DES/AES iv */
202    u_int32_t ses_keysize; /* AES key size */
203    u_int32_t ses_mlen; /* hmac/hash length */
204};
205
206struct ubsec_stats {
207    u_int64_t hst_ibytes;
208    u_int64_t hst_obytes;
209    u_int32_t hst_ipackets;
210    u_int32_t hst_opackets;
211    u_int32_t hst_invalid;
212    u_int32_t hst_nomem;
213    u_int32_t hst_queuefull;
214    u_int32_t hst_dmaerr;
215    u_int32_t hst_mcrerr;
216    u_int32_t hst_nodmafree;
217};
218
219struct ubsec_generic_ctx {
220    u_int32_t pc_key[8]; /* [3]DES/AES key */
221    u_int32_t pc_hminner[5]; /* hmac inner state */
222    u_int32_t pc_hmouter[5]; /* hmac outer state */
223    u_int32_t pc_iv[4]; /* [3]DES/AES iv */
224    u_int16_t pc_flags; /* flags, below */
225    u_int16_t pc_offset; /* crypto offset */
226    u_int16_t pc_type; /* Cryptographic operation */
227};
228
229

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