| 1 | --- a/arch/mips/ar7/platform.c |
| 2 | +++ b/arch/mips/ar7/platform.c |
| 3 | @@ -716,23 +716,35 @@ static int __init ar7_register_devices(v |
| 4 | } |
| 5 | |
| 6 | if (ar7_has_high_cpmac()) { |
| 7 | - res = fixed_phy_add(PHY_POLL, cpmac_high.id, &fixed_phy_status); |
| 8 | + res = fixed_phy_add(PHY_POLL, ar7_is_titan() ? cpmac_high_titan.id : cpmac_high.id, |
| 9 | + &fixed_phy_status); |
| 10 | if (res && res != -ENODEV) |
| 11 | return res; |
| 12 | - cpmac_get_mac(1, cpmac_high_data.dev_addr); |
| 13 | - res = platform_device_register(&cpmac_high); |
| 14 | + |
| 15 | + cpmac_get_mac(1, ar7_is_titan() ? cpmac_high_data_titan.dev_addr : |
| 16 | + cpmac_high_data.dev_addr); |
| 17 | + res = platform_device_register(ar7_is_titan() ? &cpmac_high_titan : |
| 18 | + &cpmac_high); |
| 19 | + |
| 20 | if (res) |
| 21 | return res; |
| 22 | } else { |
| 23 | - cpmac_low_data.phy_mask = 0xffffffff; |
| 24 | + if (ar7_is_titan()) |
| 25 | + cpmac_low_data_titan.phy_mask = 0xffffffff; |
| 26 | + else |
| 27 | + cpmac_low_data.phy_mask = 0xffffffff; |
| 28 | + |
| 29 | } |
| 30 | |
| 31 | - res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status); |
| 32 | + res = fixed_phy_add(PHY_POLL, ar7_is_titan() ? cpmac_low_titan.id : |
| 33 | + cpmac_low.id, &fixed_phy_status); |
| 34 | if (res && res != -ENODEV) |
| 35 | return res; |
| 36 | |
| 37 | - cpmac_get_mac(0, cpmac_low_data.dev_addr); |
| 38 | - res = platform_device_register(&cpmac_low); |
| 39 | + cpmac_get_mac(0, ar7_is_titan() ? cpmac_low_data_titan.dev_addr : |
| 40 | + cpmac_low_data.dev_addr); |
| 41 | + res = platform_device_register(ar7_is_titan() ? &cpmac_low_titan : |
| 42 | + &cpmac_low); |
| 43 | if (res) |
| 44 | return res; |
| 45 | |
| 46 | --- a/drivers/net/cpmac.c |
| 47 | +++ b/drivers/net/cpmac.c |
| 48 | @@ -1153,6 +1153,8 @@ static int __devinit cpmac_probe(struct |
| 49 | goto fail; |
| 50 | } |
| 51 | |
| 52 | + ar7_device_reset(pdata->reset_bit); |
| 53 | + |
| 54 | dev->irq = platform_get_irq_byname(pdev, "irq"); |
| 55 | |
| 56 | dev->netdev_ops = &cpmac_netdev_ops; |
| 57 | @@ -1228,7 +1230,7 @@ int __devinit cpmac_init(void) |
| 58 | cpmac_mii->reset = cpmac_mdio_reset; |
| 59 | cpmac_mii->irq = mii_irqs; |
| 60 | |
| 61 | - cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256); |
| 62 | + cpmac_mii->priv = ioremap(ar7_is_titan() ? TITAN_REGS_MDIO : AR7_REGS_MDIO, 256); |
| 63 | |
| 64 | if (!cpmac_mii->priv) { |
| 65 | printk(KERN_ERR "Can't ioremap mdio registers\n"); |
| 66 | @@ -1239,10 +1241,17 @@ int __devinit cpmac_init(void) |
| 67 | #warning FIXME: unhardcode gpio&reset bits |
| 68 | ar7_gpio_disable(26); |
| 69 | ar7_gpio_disable(27); |
| 70 | - ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); |
| 71 | - ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); |
| 72 | + |
| 73 | + if (!ar7_is_titan()) { |
| 74 | + ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); |
| 75 | + ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); |
| 76 | + } |
| 77 | ar7_device_reset(AR7_RESET_BIT_EPHY); |
| 78 | |
| 79 | + if (ar7_is_titan()) { |
| 80 | + ar7_device_reset(TITAN_RESET_BIT_EPHY1); |
| 81 | + } |
| 82 | + |
| 83 | cpmac_mii->reset(cpmac_mii); |
| 84 | |
| 85 | for (i = 0; i < 300; i++) |
| 86 | @@ -1257,7 +1266,8 @@ int __devinit cpmac_init(void) |
| 87 | mask = 0; |
| 88 | } |
| 89 | |
| 90 | - cpmac_mii->phy_mask = ~(mask | 0x80000000); |
| 91 | + cpmac_mii->phy_mask = ar7_is_titan()? ~(mask | 0x80000000 | 0x40000000): |
| 92 | + ~(mask | 0x80000000); |
| 93 | snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1"); |
| 94 | |
| 95 | res = mdiobus_register(cpmac_mii); |
| 96 | --- a/arch/mips/include/asm/mach-ar7/ar7.h |
| 97 | +++ b/arch/mips/include/asm/mach-ar7/ar7.h |
| 98 | @@ -50,8 +50,10 @@ |
| 99 | #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) |
| 100 | #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) |
| 101 | |
| 102 | -#define TITAN_REGS_MAC0 (0x08640000) |
| 103 | -#define TITAN_REGS_MAC1 (TITAN_REGS_MAC0 + 0x0800) |
| 104 | +#define TITAN_REGS_ESWITCH_BASE (0x08640000) |
| 105 | +#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE + 0) |
| 106 | +#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800) |
| 107 | +#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000) |
| 108 | #define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00) |
| 109 | #define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300) |
| 110 | |
| 111 | |
