Root/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c

1/*
2 * Atheros AR71xx SoC specific interrupt handling
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18
19#include <asm/irq_cpu.h>
20#include <asm/mipsregs.h>
21
22#include <asm/mach-ar71xx/ar71xx.h>
23
24static int ip2_flush_reg;
25
26static void ar71xx_gpio_irq_dispatch(void)
27{
28    void __iomem *base = ar71xx_gpio_base;
29    u32 pending;
30
31    pending = __raw_readl(base + GPIO_REG_INT_PENDING) &
32          __raw_readl(base + GPIO_REG_INT_ENABLE);
33
34    if (pending)
35        do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
36    else
37        spurious_interrupt();
38}
39
40static void ar71xx_gpio_irq_unmask(unsigned int irq)
41{
42    void __iomem *base = ar71xx_gpio_base;
43    u32 t;
44
45    irq -= AR71XX_GPIO_IRQ_BASE;
46
47    t = __raw_readl(base + GPIO_REG_INT_ENABLE);
48    __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE);
49
50    /* flush write */
51    (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
52}
53
54static void ar71xx_gpio_irq_mask(unsigned int irq)
55{
56    void __iomem *base = ar71xx_gpio_base;
57    u32 t;
58
59    irq -= AR71XX_GPIO_IRQ_BASE;
60
61    t = __raw_readl(base + GPIO_REG_INT_ENABLE);
62    __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE);
63
64    /* flush write */
65    (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
66}
67
68#if 0
69static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
70{
71    /* TODO: implement */
72    return 0;
73}
74#else
75#define ar71xx_gpio_irq_set_type NULL
76#endif
77
78static struct irq_chip ar71xx_gpio_irq_chip = {
79    .name = "AR71XX GPIO",
80    .unmask = ar71xx_gpio_irq_unmask,
81    .mask = ar71xx_gpio_irq_mask,
82    .mask_ack = ar71xx_gpio_irq_mask,
83    .set_type = ar71xx_gpio_irq_set_type,
84};
85
86static struct irqaction ar71xx_gpio_irqaction = {
87    .handler = no_action,
88    .name = "cascade [AR71XX GPIO]",
89};
90
91#define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
92#define GPIO_INT_ALL 0xffff
93
94static void __init ar71xx_gpio_irq_init(void)
95{
96    void __iomem *base = ar71xx_gpio_base;
97    int i;
98
99    __raw_writel(0, base + GPIO_REG_INT_ENABLE);
100    __raw_writel(0, base + GPIO_REG_INT_PENDING);
101
102    /* setup type of all GPIO interrupts to level sensitive */
103    __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE);
104
105    /* setup polarity of all GPIO interrupts to active high */
106    __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY);
107
108    for (i = AR71XX_GPIO_IRQ_BASE;
109         i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
110        irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
111        set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
112                     handle_level_irq);
113    }
114
115    setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
116}
117
118static void ar71xx_misc_irq_dispatch(void)
119{
120    u32 pending;
121
122    pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
123        & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
124
125    if (pending & MISC_INT_UART)
126        do_IRQ(AR71XX_MISC_IRQ_UART);
127
128    else if (pending & MISC_INT_DMA)
129        do_IRQ(AR71XX_MISC_IRQ_DMA);
130
131    else if (pending & MISC_INT_PERFC)
132        do_IRQ(AR71XX_MISC_IRQ_PERFC);
133
134    else if (pending & MISC_INT_TIMER)
135        do_IRQ(AR71XX_MISC_IRQ_TIMER);
136
137    else if (pending & MISC_INT_OHCI)
138        do_IRQ(AR71XX_MISC_IRQ_OHCI);
139
140    else if (pending & MISC_INT_ERROR)
141        do_IRQ(AR71XX_MISC_IRQ_ERROR);
142
143    else if (pending & MISC_INT_GPIO)
144        ar71xx_gpio_irq_dispatch();
145
146    else if (pending & MISC_INT_WDOG)
147        do_IRQ(AR71XX_MISC_IRQ_WDOG);
148
149    else
150        spurious_interrupt();
151}
152
153static void ar71xx_misc_irq_unmask(unsigned int irq)
154{
155    void __iomem *base = ar71xx_reset_base;
156    u32 t;
157
158    irq -= AR71XX_MISC_IRQ_BASE;
159
160    t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
161    __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
162
163    /* flush write */
164    (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
165}
166
167static void ar71xx_misc_irq_mask(unsigned int irq)
168{
169    void __iomem *base = ar71xx_reset_base;
170    u32 t;
171
172    irq -= AR71XX_MISC_IRQ_BASE;
173
174    t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
175    __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
176
177    /* flush write */
178    (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
179}
180
181static void ar724x_misc_irq_ack(unsigned int irq)
182{
183    void __iomem *base = ar71xx_reset_base;
184    u32 t;
185
186    irq -= AR71XX_MISC_IRQ_BASE;
187
188    t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
189    __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
190
191    /* flush write */
192    (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
193}
194
195static struct irq_chip ar71xx_misc_irq_chip = {
196    .name = "AR71XX MISC",
197    .unmask = ar71xx_misc_irq_unmask,
198    .mask = ar71xx_misc_irq_mask,
199};
200
201static struct irqaction ar71xx_misc_irqaction = {
202    .handler = no_action,
203    .name = "cascade [AR71XX MISC]",
204};
205
206static void __init ar71xx_misc_irq_init(void)
207{
208    void __iomem *base = ar71xx_reset_base;
209    int i;
210
211    __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
212    __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
213
214    switch (ar71xx_soc) {
215    case AR71XX_SOC_AR7240:
216    case AR71XX_SOC_AR7241:
217    case AR71XX_SOC_AR7242:
218        ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
219        break;
220    default:
221        ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
222        break;
223    }
224
225    for (i = AR71XX_MISC_IRQ_BASE;
226         i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
227        irq_desc[i].status = IRQ_DISABLED;
228        set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
229                     handle_level_irq);
230    }
231
232    setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
233}
234
235asmlinkage void plat_irq_dispatch(void)
236{
237    unsigned long pending;
238
239    pending = read_c0_status() & read_c0_cause() & ST0_IM;
240
241    if (pending & STATUSF_IP7)
242        do_IRQ(AR71XX_CPU_IRQ_TIMER);
243
244    else if (pending & STATUSF_IP2) {
245        /*
246         * This IRQ is meant for a PCI device. Drivers for PCI devices
247         * typically allocate coherent DMA memory for the descriptor
248         * ring, however the DMA controller may still have some
249         * unsynchronized data in the FIFO.
250         * Issue a flush here to ensure that the driver sees the update.
251         */
252        ar71xx_ddr_flush(ip2_flush_reg);
253        do_IRQ(AR71XX_CPU_IRQ_IP2);
254    }
255
256    else if (pending & STATUSF_IP4)
257        do_IRQ(AR71XX_CPU_IRQ_GE0);
258
259    else if (pending & STATUSF_IP5)
260        do_IRQ(AR71XX_CPU_IRQ_GE1);
261
262    else if (pending & STATUSF_IP3)
263        do_IRQ(AR71XX_CPU_IRQ_USB);
264
265    else if (pending & STATUSF_IP6)
266        ar71xx_misc_irq_dispatch();
267
268    else
269        spurious_interrupt();
270}
271
272void __init arch_init_irq(void)
273{
274    switch(ar71xx_soc) {
275    case AR71XX_SOC_AR7240:
276    case AR71XX_SOC_AR7241:
277    case AR71XX_SOC_AR7242:
278        ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
279        break;
280    case AR71XX_SOC_AR9130:
281    case AR71XX_SOC_AR9132:
282        ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC;
283        break;
284    default:
285        ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
286        break;
287    }
288    mips_cpu_irq_init();
289
290    ar71xx_misc_irq_init();
291
292    cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
293
294    ar71xx_gpio_irq_init();
295}
296

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