Root/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c

1/*
2 * Atheros AR724x PCI host controller driver
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * Parts of this file are based on Atheros' 2.6.15 BSP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#include <linux/resource.h>
14#include <linux/types.h>
15#include <linux/delay.h>
16#include <linux/bitops.h>
17#include <linux/pci.h>
18#include <linux/pci_regs.h>
19#include <linux/interrupt.h>
20
21#include <asm/mach-ar71xx/ar71xx.h>
22#include <asm/mach-ar71xx/pci.h>
23
24#undef DEBUG
25#ifdef DEBUG
26#define DBG(fmt, args...) printk(KERN_INFO fmt, ## args)
27#else
28#define DBG(fmt, args...)
29#endif
30
31static void __iomem *ar724x_pci_localcfg_base;
32static void __iomem *ar724x_pci_devcfg_base;
33static void __iomem *ar724x_pci_ctrl_base;
34static int ar724x_pci_fixup_enable;
35
36static DEFINE_SPINLOCK(ar724x_pci_lock);
37
38static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
39{
40    unsigned long flags;
41    u32 data;
42
43    spin_lock_irqsave(&ar724x_pci_lock, flags);
44    data = __raw_readl(base + (where & ~3));
45
46    switch (size) {
47    case 1:
48        if (where & 1)
49            data >>= 8;
50        if (where & 2)
51            data >>= 16;
52        data &= 0xFF;
53        break;
54    case 2:
55        if (where & 2)
56            data >>= 16;
57        data &= 0xFFFF;
58        break;
59    }
60
61    *value = data;
62    spin_unlock_irqrestore(&ar724x_pci_lock, flags);
63}
64
65static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
66{
67    unsigned long flags;
68    u32 data;
69    int s;
70
71    spin_lock_irqsave(&ar724x_pci_lock, flags);
72    data = __raw_readl(base + (where & ~3));
73
74    switch (size) {
75    case 1:
76        s = ((where & 3) << 3);
77        data &= ~(0xFF << s);
78        data |= ((value & 0xFF) << s);
79        break;
80    case 2:
81        s = ((where & 2) << 3);
82        data &= ~(0xFFFF << s);
83        data |= ((value & 0xFFFF) << s);
84        break;
85    case 4:
86        data = value;
87        break;
88    }
89
90    __raw_writel(data, base + (where & ~3));
91    /* flush write */
92    (void)__raw_readl(base + (where & ~3));
93    spin_unlock_irqrestore(&ar724x_pci_lock, flags);
94}
95
96static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
97                  int where, int size, u32 *value)
98{
99
100    if (bus->number != 0 || devfn != 0)
101        return PCIBIOS_DEVICE_NOT_FOUND;
102
103    ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
104
105    DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
106            bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
107            where, size, *value);
108
109    /*
110     * WAR for BAR issue - We are unable to access the PCI device space
111     * if we set the BAR with proper base address
112     */
113    if ((where == 0x10) && (size == 4)) {
114        if (ar71xx_soc == AR71XX_SOC_AR7240)
115            ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
116        else
117            ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0x1000ffff);
118    }
119
120    return PCIBIOS_SUCCESSFUL;
121}
122
123static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
124                   int where, int size, u32 value)
125{
126    if (bus->number != 0 || devfn != 0)
127        return PCIBIOS_DEVICE_NOT_FOUND;
128
129    DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
130        bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
131        where, size, value);
132
133    ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
134
135    return PCIBIOS_SUCCESSFUL;
136}
137
138static void ar724x_pci_fixup(struct pci_dev *dev)
139{
140    u16 cmd;
141
142    if (!ar724x_pci_fixup_enable)
143        return;
144
145    if (dev->bus->number != 0 || dev->devfn != 0)
146        return;
147
148    /* setup COMMAND register */
149    pci_read_config_word(dev, PCI_COMMAND, &cmd);
150    cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
151           PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
152           PCI_COMMAND_FAST_BACK;
153
154    pci_write_config_word(dev, PCI_COMMAND, cmd);
155}
156DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
157
158int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
159                  uint8_t pin)
160{
161    int irq = -1;
162    int i;
163
164    for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
165        struct ar71xx_pci_irq *entry;
166        entry = &ar71xx_pci_irq_map[i];
167
168        if (entry->slot == slot && entry->pin == pin) {
169            irq = entry->irq;
170            break;
171        }
172    }
173
174    if (irq < 0)
175        printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
176                pin, pci_name((struct pci_dev *)dev));
177    else
178        printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
179                irq, pin, pci_name((struct pci_dev *)dev));
180
181    return irq;
182}
183
184static struct pci_ops ar724x_pci_ops = {
185    .read = ar724x_pci_read_config,
186    .write = ar724x_pci_write_config,
187};
188
189static struct resource ar724x_pci_io_resource = {
190    .name = "PCI IO space",
191    .start = 0,
192    .end = 0,
193    .flags = IORESOURCE_IO,
194};
195
196static struct resource ar724x_pci_mem_resource = {
197    .name = "PCI memory space",
198    .start = AR71XX_PCI_MEM_BASE,
199    .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
200    .flags = IORESOURCE_MEM
201};
202
203static struct pci_controller ar724x_pci_controller = {
204    .pci_ops = &ar724x_pci_ops,
205    .mem_resource = &ar724x_pci_mem_resource,
206    .io_resource = &ar724x_pci_io_resource,
207};
208
209static void __init ar724x_pci_reset(void)
210{
211    ar71xx_device_stop(AR724X_RESET_PCIE);
212    ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
213    ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
214    udelay(100);
215
216    ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
217    udelay(100);
218    ar71xx_device_start(AR724X_RESET_PCIE_PHY);
219    ar71xx_device_start(AR724X_RESET_PCIE);
220}
221
222static int __init ar724x_pci_setup(void)
223{
224    void __iomem *base = ar724x_pci_ctrl_base;
225    u32 t;
226
227    /* setup COMMAND register */
228    t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
229        PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
230
231    ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
232    ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
233    ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
234
235    t = __raw_readl(base + AR724X_PCI_REG_RESET);
236    if (t != 0x7) {
237        udelay(100000);
238        __raw_writel(0, base + AR724X_PCI_REG_RESET);
239        udelay(100);
240        __raw_writel(4, base + AR724X_PCI_REG_RESET);
241        udelay(100000);
242    }
243
244    if (ar71xx_soc == AR71XX_SOC_AR7240)
245        t = AR724X_PCI_APP_LTSSM_ENABLE;
246    else
247        t = 0x1ffc1;
248    __raw_writel(t, base + AR724X_PCI_REG_APP);
249    /* flush write */
250    (void) __raw_readl(base + AR724X_PCI_REG_APP);
251    udelay(1000);
252
253    t = __raw_readl(base + AR724X_PCI_REG_RESET);
254    if ((t & AR724X_PCI_RESET_LINK_UP) == 0x0) {
255        printk(KERN_WARNING "PCI: no PCIe module found\n");
256        return -ENODEV;
257    }
258
259    if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) {
260        t = __raw_readl(base + AR724X_PCI_REG_APP);
261        t |= BIT(16);
262        __raw_writel(t, base + AR724X_PCI_REG_APP);
263    }
264
265    return 0;
266}
267
268static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
269{
270    void __iomem *base = ar724x_pci_ctrl_base;
271    u32 pending;
272
273    pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
274          __raw_readl(base + AR724X_PCI_REG_INT_MASK);
275
276    if (pending & AR724X_PCI_INT_DEV0)
277        generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
278
279    else
280        spurious_interrupt();
281}
282
283static void ar724x_pci_irq_unmask(unsigned int irq)
284{
285    void __iomem *base = ar724x_pci_ctrl_base;
286    u32 t;
287
288    switch (irq) {
289    case AR71XX_PCI_IRQ_DEV0:
290        irq -= AR71XX_PCI_IRQ_BASE;
291
292        t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
293        __raw_writel(t | AR724X_PCI_INT_DEV0,
294                 base + AR724X_PCI_REG_INT_MASK);
295        /* flush write */
296        (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK);
297    }
298}
299
300static void ar724x_pci_irq_mask(unsigned int irq)
301{
302    void __iomem *base = ar724x_pci_ctrl_base;
303    u32 t;
304
305    switch (irq) {
306    case AR71XX_PCI_IRQ_DEV0:
307        irq -= AR71XX_PCI_IRQ_BASE;
308
309        t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
310        __raw_writel(t & ~AR724X_PCI_INT_DEV0,
311                 base + AR724X_PCI_REG_INT_MASK);
312
313        /* flush write */
314        (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK);
315
316        t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
317        __raw_writel(t | AR724X_PCI_INT_DEV0,
318                 base + AR724X_PCI_REG_INT_STATUS);
319
320        /* flush write */
321        (void) __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
322    }
323}
324
325static struct irq_chip ar724x_pci_irq_chip = {
326    .name = "AR724X PCI ",
327    .mask = ar724x_pci_irq_mask,
328    .unmask = ar724x_pci_irq_unmask,
329    .mask_ack = ar724x_pci_irq_mask,
330};
331
332static void __init ar724x_pci_irq_init(void)
333{
334    void __iomem *base = ar724x_pci_ctrl_base;
335    u32 t;
336    int i;
337
338    t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
339    if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
340         AR724X_RESET_PCIE_PHY_SERIAL)) {
341        return;
342    }
343
344    __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
345    __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
346
347    for (i = AR71XX_PCI_IRQ_BASE;
348         i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
349        irq_desc[i].status = IRQ_DISABLED;
350        set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
351                     handle_level_irq);
352    }
353
354    set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler);
355}
356
357int __init ar724x_pcibios_init(void)
358{
359    int ret = -ENOMEM;
360
361    ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
362                           AR724X_PCI_CRP_SIZE);
363    if (ar724x_pci_localcfg_base == NULL)
364        goto err;
365
366    ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
367                         AR724X_PCI_CFG_SIZE);
368    if (ar724x_pci_devcfg_base == NULL)
369        goto err_unmap_localcfg;
370
371    ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE,
372                           AR724X_PCI_CTRL_SIZE);
373    if (ar724x_pci_ctrl_base == NULL)
374        goto err_unmap_devcfg;
375
376    ar724x_pci_reset();
377    ret = ar724x_pci_setup();
378    if (ret)
379        goto err_unmap_ctrl;
380
381    ar724x_pci_fixup_enable = 1;
382    ar724x_pci_irq_init();
383    register_pci_controller(&ar724x_pci_controller);
384
385    return 0;
386
387 err_unmap_ctrl:
388    iounmap(ar724x_pci_ctrl_base);
389  err_unmap_devcfg:
390    iounmap(ar724x_pci_devcfg_base);
391 err_unmap_localcfg:
392    iounmap(ar724x_pci_localcfg_base);
393 err:
394    return ret;
395}
396

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