Root/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h

1/*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#ifndef __AG71XX_H
15#define __AG71XX_H
16
17#include <linux/kernel.h>
18#include <linux/version.h>
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/types.h>
22#include <linux/random.h>
23#include <linux/spinlock.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
26#include <linux/ethtool.h>
27#include <linux/etherdevice.h>
28#include <linux/phy.h>
29#include <linux/skbuff.h>
30#include <linux/dma-mapping.h>
31#include <linux/workqueue.h>
32
33#include <linux/bitops.h>
34
35#include <asm/mach-ar71xx/ar71xx.h>
36#include <asm/mach-ar71xx/platform.h>
37
38#define ETH_FCS_LEN 4
39
40#define AG71XX_DRV_NAME "ag71xx"
41#define AG71XX_DRV_VERSION "0.5.35"
42
43#define AG71XX_NAPI_WEIGHT 64
44#define AG71XX_OOM_REFILL (1 + HZ/10)
45
46#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
47#define AG71XX_INT_TX (AG71XX_INT_TX_PS)
48#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49
50#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
51#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
52
53#define AG71XX_TX_FIFO_LEN 2048
54#define AG71XX_TX_MTU_LEN 1540
55#define AG71XX_RX_PKT_RESERVE 64
56#define AG71XX_RX_PKT_SIZE \
57    (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
58
59#define AG71XX_TX_RING_SIZE 64
60#define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
61#define AG71XX_TX_THRES_WAKEUP \
62        (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
63
64#define AG71XX_RX_RING_SIZE 128
65
66#ifdef CONFIG_AG71XX_DEBUG
67#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
68#else
69#define DBG(fmt, args...) do {} while (0)
70#endif
71
72#define ag71xx_assert(_cond) \
73do { \
74    if (_cond) \
75        break; \
76    printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
77    BUG(); \
78} while (0)
79
80struct ag71xx_desc {
81    u32 data;
82    u32 ctrl;
83#define DESC_EMPTY BIT(31)
84#define DESC_MORE BIT(24)
85#define DESC_PKTLEN_M 0xfff
86    u32 next;
87    u32 pad;
88} __attribute__((aligned(4)));
89
90struct ag71xx_buf {
91    struct sk_buff *skb;
92    struct ag71xx_desc *desc;
93    dma_addr_t dma_addr;
94    u32 pad;
95};
96
97struct ag71xx_ring {
98    struct ag71xx_buf *buf;
99    u8 *descs_cpu;
100    dma_addr_t descs_dma;
101    unsigned int desc_size;
102    unsigned int curr;
103    unsigned int dirty;
104    unsigned int size;
105};
106
107struct ag71xx_mdio {
108    struct mii_bus *mii_bus;
109    int mii_irq[PHY_MAX_ADDR];
110    void __iomem *mdio_base;
111    struct ag71xx_mdio_platform_data *pdata;
112};
113
114struct ag71xx_int_stats {
115    unsigned long rx_pr;
116    unsigned long rx_be;
117    unsigned long rx_of;
118    unsigned long tx_ps;
119    unsigned long tx_be;
120    unsigned long tx_ur;
121    unsigned long total;
122};
123
124struct ag71xx_napi_stats {
125    unsigned long napi_calls;
126    unsigned long rx_count;
127    unsigned long rx_packets;
128    unsigned long rx_packets_max;
129    unsigned long tx_count;
130    unsigned long tx_packets;
131    unsigned long tx_packets_max;
132
133    unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
134    unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
135};
136
137struct ag71xx_debug {
138    struct dentry *debugfs_dir;
139    struct dentry *debugfs_int_stats;
140    struct dentry *debugfs_napi_stats;
141
142    struct ag71xx_int_stats int_stats;
143    struct ag71xx_napi_stats napi_stats;
144};
145
146struct ag71xx {
147    void __iomem *mac_base;
148    void __iomem *mii_ctrl;
149
150    spinlock_t lock;
151    struct platform_device *pdev;
152    struct net_device *dev;
153    struct napi_struct napi;
154    u32 msg_enable;
155
156    struct ag71xx_ring rx_ring;
157    struct ag71xx_ring tx_ring;
158
159    struct mii_bus *mii_bus;
160    struct phy_device *phy_dev;
161    void *phy_priv;
162
163    unsigned int link;
164    unsigned int speed;
165    int duplex;
166
167    struct work_struct restart_work;
168    struct timer_list oom_timer;
169
170#ifdef CONFIG_AG71XX_DEBUG_FS
171    struct ag71xx_debug debug;
172#endif
173};
174
175extern struct ethtool_ops ag71xx_ethtool_ops;
176void ag71xx_link_adjust(struct ag71xx *ag);
177
178int ag71xx_mdio_driver_init(void) __init;
179void ag71xx_mdio_driver_exit(void);
180
181int ag71xx_phy_connect(struct ag71xx *ag);
182void ag71xx_phy_disconnect(struct ag71xx *ag);
183void ag71xx_phy_start(struct ag71xx *ag);
184void ag71xx_phy_stop(struct ag71xx *ag);
185
186static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
187{
188    return ag->pdev->dev.platform_data;
189}
190
191static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
192{
193    return (desc->ctrl & DESC_EMPTY) != 0;
194}
195
196static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
197{
198    return desc->ctrl & DESC_PKTLEN_M;
199}
200
201/* Register offsets */
202#define AG71XX_REG_MAC_CFG1 0x0000
203#define AG71XX_REG_MAC_CFG2 0x0004
204#define AG71XX_REG_MAC_IPG 0x0008
205#define AG71XX_REG_MAC_HDX 0x000c
206#define AG71XX_REG_MAC_MFL 0x0010
207#define AG71XX_REG_MII_CFG 0x0020
208#define AG71XX_REG_MII_CMD 0x0024
209#define AG71XX_REG_MII_ADDR 0x0028
210#define AG71XX_REG_MII_CTRL 0x002c
211#define AG71XX_REG_MII_STATUS 0x0030
212#define AG71XX_REG_MII_IND 0x0034
213#define AG71XX_REG_MAC_IFCTL 0x0038
214#define AG71XX_REG_MAC_ADDR1 0x0040
215#define AG71XX_REG_MAC_ADDR2 0x0044
216#define AG71XX_REG_FIFO_CFG0 0x0048
217#define AG71XX_REG_FIFO_CFG1 0x004c
218#define AG71XX_REG_FIFO_CFG2 0x0050
219#define AG71XX_REG_FIFO_CFG3 0x0054
220#define AG71XX_REG_FIFO_CFG4 0x0058
221#define AG71XX_REG_FIFO_CFG5 0x005c
222#define AG71XX_REG_FIFO_RAM0 0x0060
223#define AG71XX_REG_FIFO_RAM1 0x0064
224#define AG71XX_REG_FIFO_RAM2 0x0068
225#define AG71XX_REG_FIFO_RAM3 0x006c
226#define AG71XX_REG_FIFO_RAM4 0x0070
227#define AG71XX_REG_FIFO_RAM5 0x0074
228#define AG71XX_REG_FIFO_RAM6 0x0078
229#define AG71XX_REG_FIFO_RAM7 0x007c
230
231#define AG71XX_REG_TX_CTRL 0x0180
232#define AG71XX_REG_TX_DESC 0x0184
233#define AG71XX_REG_TX_STATUS 0x0188
234#define AG71XX_REG_RX_CTRL 0x018c
235#define AG71XX_REG_RX_DESC 0x0190
236#define AG71XX_REG_RX_STATUS 0x0194
237#define AG71XX_REG_INT_ENABLE 0x0198
238#define AG71XX_REG_INT_STATUS 0x019c
239
240#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
241#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
242#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
243#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
244#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
245#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
246#define MAC_CFG1_LB BIT(8) /* Loopback mode */
247#define MAC_CFG1_SR BIT(31) /* Soft Reset */
248
249#define MAC_CFG2_FDX BIT(0)
250#define MAC_CFG2_CRC_EN BIT(1)
251#define MAC_CFG2_PAD_CRC_EN BIT(2)
252#define MAC_CFG2_LEN_CHECK BIT(4)
253#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
254#define MAC_CFG2_IF_1000 BIT(9)
255#define MAC_CFG2_IF_10_100 BIT(8)
256
257#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
258#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
259#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
260#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
261#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
262#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
263            | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
264
265#define FIFO_CFG0_ENABLE_SHIFT 8
266
267#define FIFO_CFG4_DE BIT(0) /* Drop Event */
268#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
269#define FIFO_CFG4_FC BIT(2) /* False Carrier */
270#define FIFO_CFG4_CE BIT(3) /* Code Error */
271#define FIFO_CFG4_CR BIT(4) /* CRC error */
272#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
273#define FIFO_CFG4_LO BIT(6) /* Length out of range */
274#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
275#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
276#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
277#define FIFO_CFG4_DR BIT(10) /* Dribble */
278#define FIFO_CFG4_LE BIT(11) /* Long Event */
279#define FIFO_CFG4_CF BIT(12) /* Control Frame */
280#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
281#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
282#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
283#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
284#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
285
286#define FIFO_CFG5_DE BIT(0) /* Drop Event */
287#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
288#define FIFO_CFG5_FC BIT(2) /* False Carrier */
289#define FIFO_CFG5_CE BIT(3) /* Code Error */
290#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
291#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
292#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
293#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
294#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
295#define FIFO_CFG5_DR BIT(9) /* Dribble */
296#define FIFO_CFG5_CF BIT(10) /* Control Frame */
297#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
298#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
299#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
300#define FIFO_CFG5_LE BIT(14) /* Long Event */
301#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
302#define FIFO_CFG5_16 BIT(16) /* unknown */
303#define FIFO_CFG5_17 BIT(17) /* unknown */
304#define FIFO_CFG5_SF BIT(18) /* Short Frame */
305#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
306
307#define AG71XX_INT_TX_PS BIT(0)
308#define AG71XX_INT_TX_UR BIT(1)
309#define AG71XX_INT_TX_BE BIT(3)
310#define AG71XX_INT_RX_PR BIT(4)
311#define AG71XX_INT_RX_OF BIT(6)
312#define AG71XX_INT_RX_BE BIT(7)
313
314#define MAC_IFCTL_SPEED BIT(16)
315
316#define MII_CFG_CLK_DIV_4 0
317#define MII_CFG_CLK_DIV_6 2
318#define MII_CFG_CLK_DIV_8 3
319#define MII_CFG_CLK_DIV_10 4
320#define MII_CFG_CLK_DIV_14 5
321#define MII_CFG_CLK_DIV_20 6
322#define MII_CFG_CLK_DIV_28 7
323#define MII_CFG_RESET BIT(31)
324
325#define MII_CMD_WRITE 0x0
326#define MII_CMD_READ 0x1
327#define MII_ADDR_SHIFT 8
328#define MII_IND_BUSY BIT(0)
329#define MII_IND_INVALID BIT(2)
330
331#define TX_CTRL_TXE BIT(0) /* Tx Enable */
332
333#define TX_STATUS_PS BIT(0) /* Packet Sent */
334#define TX_STATUS_UR BIT(1) /* Tx Underrun */
335#define TX_STATUS_BE BIT(3) /* Bus Error */
336
337#define RX_CTRL_RXE BIT(0) /* Rx Enable */
338
339#define RX_STATUS_PR BIT(0) /* Packet Received */
340#define RX_STATUS_OF BIT(2) /* Rx Overflow */
341#define RX_STATUS_BE BIT(3) /* Bus Error */
342
343#define MII_CTRL_IF_MASK 3
344#define MII_CTRL_SPEED_SHIFT 4
345#define MII_CTRL_SPEED_MASK 3
346#define MII_CTRL_SPEED_10 0
347#define MII_CTRL_SPEED_100 1
348#define MII_CTRL_SPEED_1000 2
349
350static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
351{
352    switch (reg) {
353    case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
354    case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
355        break;
356
357    default:
358        BUG();
359    }
360}
361
362static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
363{
364    ag71xx_check_reg_offset(ag, reg);
365
366    __raw_writel(value, ag->mac_base + reg);
367    /* flush write */
368    (void) __raw_readl(ag->mac_base + reg);
369}
370
371static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
372{
373    ag71xx_check_reg_offset(ag, reg);
374
375    return __raw_readl(ag->mac_base + reg);
376}
377
378static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
379{
380    void __iomem *r;
381
382    ag71xx_check_reg_offset(ag, reg);
383
384    r = ag->mac_base + reg;
385    __raw_writel(__raw_readl(r) | mask, r);
386    /* flush write */
387    (void)__raw_readl(r);
388}
389
390static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
391{
392    void __iomem *r;
393
394    ag71xx_check_reg_offset(ag, reg);
395
396    r = ag->mac_base + reg;
397    __raw_writel(__raw_readl(r) & ~mask, r);
398    /* flush write */
399    (void) __raw_readl(r);
400}
401
402static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
403{
404    ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
405}
406
407static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
408{
409    ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
410}
411
412static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
413{
414    struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
415
416    if (pdata->is_ar724x)
417        return;
418
419    __raw_writel(value, ag->mii_ctrl);
420
421    /* flush write */
422    __raw_readl(ag->mii_ctrl);
423}
424
425static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
426{
427    struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
428
429    if (pdata->is_ar724x)
430        return 0xffffffff;
431
432    return __raw_readl(ag->mii_ctrl);
433}
434
435static inline void ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
436                      unsigned int mii_if)
437{
438    u32 t;
439
440    t = ag71xx_mii_ctrl_rr(ag);
441    t &= ~(MII_CTRL_IF_MASK);
442    t |= (mii_if & MII_CTRL_IF_MASK);
443    ag71xx_mii_ctrl_wr(ag, t);
444}
445
446static inline void ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
447                         unsigned int speed)
448{
449    u32 t;
450
451    t = ag71xx_mii_ctrl_rr(ag);
452    t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
453    t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
454    ag71xx_mii_ctrl_wr(ag, t);
455}
456
457#ifdef CONFIG_AG71XX_AR8216_SUPPORT
458void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
459int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
460                int pktlen);
461static inline int ag71xx_has_ar8216(struct ag71xx *ag)
462{
463    return ag71xx_get_pdata(ag)->has_ar8216;
464}
465#else
466static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
467                       struct sk_buff *skb)
468{
469}
470
471static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
472                          struct sk_buff *skb,
473                          int pktlen)
474{
475    return 0;
476}
477static inline int ag71xx_has_ar8216(struct ag71xx *ag)
478{
479    return 0;
480}
481#endif
482
483#ifdef CONFIG_AG71XX_DEBUG_FS
484int ag71xx_debugfs_root_init(void);
485void ag71xx_debugfs_root_exit(void);
486int ag71xx_debugfs_init(struct ag71xx *ag);
487void ag71xx_debugfs_exit(struct ag71xx *ag);
488void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
489void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
490#else
491static inline int ag71xx_debugfs_root_init(void) { return 0; }
492static inline void ag71xx_debugfs_root_exit(void) {}
493static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
494static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
495static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
496                           u32 status) {}
497static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
498                            int rx, int tx) {}
499#endif /* CONFIG_AG71XX_DEBUG_FS */
500
501void ag71xx_ar7240_start(struct ag71xx *ag);
502void ag71xx_ar7240_stop(struct ag71xx *ag);
503int ag71xx_ar7240_init(struct ag71xx *ag);
504void ag71xx_ar7240_cleanup(struct ag71xx *ag);
505
506int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
507void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
508
509u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
510              unsigned reg_addr);
511int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
512               unsigned reg_addr, u16 reg_val);
513
514#endif /* _AG71XX_H */
515

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