Root/target/linux/ar71xx/files/drivers/spi/spi_vsc7385.c

1/*
2 * SPI driver for the Vitesse VSC7385 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * Parts of this file are based on Atheros' 2.6.15 BSP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/bitops.h>
20#include <linux/firmware.h>
21#include <linux/spi/spi.h>
22#include <linux/spi/vsc7385.h>
23
24#define DRV_NAME "spi-vsc7385"
25#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver"
26#define DRV_VERSION "0.1.0"
27
28#define VSC73XX_BLOCK_MAC 0x1
29#define VSC73XX_BLOCK_2 0x2
30#define VSC73XX_BLOCK_MII 0x3
31#define VSC73XX_BLOCK_4 0x4
32#define VSC73XX_BLOCK_5 0x5
33#define VSC73XX_BLOCK_SYSTEM 0x7
34
35#define VSC73XX_SUBBLOCK_PORT_0 0
36#define VSC73XX_SUBBLOCK_PORT_1 1
37#define VSC73XX_SUBBLOCK_PORT_2 2
38#define VSC73XX_SUBBLOCK_PORT_3 3
39#define VSC73XX_SUBBLOCK_PORT_4 4
40#define VSC73XX_SUBBLOCK_PORT_MAC 6
41
42/* MAC Block registers */
43#define VSC73XX_MAC_CFG 0x0
44#define VSC73XX_ADVPORTM 0x19
45#define VSC73XX_RXOCT 0x50
46#define VSC73XX_TXOCT 0x51
47#define VSC73XX_C_RX0 0x52
48#define VSC73XX_C_RX1 0x53
49#define VSC73XX_C_RX2 0x54
50#define VSC73XX_C_TX0 0x55
51#define VSC73XX_C_TX1 0x56
52#define VSC73XX_C_TX2 0x57
53#define VSC73XX_C_CFG 0x58
54
55/* MAC_CFG register bits */
56#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31)
57#define VSC73XX_MAC_CFG_PORT_RST (1 << 29)
58#define VSC73XX_MAC_CFG_TX_EN (1 << 28)
59#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27)
60#define VSC73XX_MAC_CFG_FDX (1 << 18)
61#define VSC73XX_MAC_CFG_GIGE (1 << 17)
62#define VSC73XX_MAC_CFG_RX_EN (1 << 16)
63#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15)
64#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14)
65#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13)
66#define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6)
67#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5)
68#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4)
69#define VSC73XX_MAC_CFG_BIT2 (1 << 2)
70#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3)
71
72/* ADVPORTM register bits */
73#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7)
74#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6)
75#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5)
76#define VSC73XX_ADVPORTM_INV_GTX (1 << 4)
77#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3)
78#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2)
79#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1)
80#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0)
81
82/* MII Block registers */
83#define VSC73XX_MII_STAT 0x0
84#define VSC73XX_MII_CMD 0x1
85#define VSC73XX_MII_DATA 0x2
86
87/* System Block registers */
88#define VSC73XX_ICPU_SIPAD 0x01
89#define VSC73XX_ICPU_CLOCK_DELAY 0x05
90#define VSC73XX_ICPU_CTRL 0x10
91#define VSC73XX_ICPU_ADDR 0x11
92#define VSC73XX_ICPU_SRAM 0x12
93#define VSC73XX_ICPU_MBOX_VAL 0x15
94#define VSC73XX_ICPU_MBOX_SET 0x16
95#define VSC73XX_ICPU_MBOX_CLR 0x17
96#define VSC73XX_ICPU_CHIPID 0x18
97#define VSC73XX_ICPU_GPIO 0x34
98
99#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8)
100#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7)
101#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3)
102#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2)
103#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1)
104#define VSC73XX_ICPU_CTRL_SRST (1 << 0)
105
106#define VSC73XX_ICPU_CHIPID_ID_SHIFT 12
107#define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff
108#define VSC73XX_ICPU_CHIPID_REV_SHIFT 28
109#define VSC73XX_ICPU_CHIPID_REV_MASK 0xf
110#define VSC73XX_ICPU_CHIPID_ID_7385 0x7385
111#define VSC73XX_ICPU_CHIPID_ID_7395 0x7395
112
113#define VSC73XX_CMD_MODE_READ 0
114#define VSC73XX_CMD_MODE_WRITE 1
115#define VSC73XX_CMD_MODE_SHIFT 4
116#define VSC73XX_CMD_BLOCK_SHIFT 5
117#define VSC73XX_CMD_BLOCK_MASK 0x7
118#define VSC73XX_CMD_SUBBLOCK_MASK 0xf
119
120#define VSC7385_CLOCK_DELAY ((3 << 4) | 3)
121#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3)
122
123#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \
124                 VSC73XX_ICPU_CTRL_BOOT_EN | \
125                 VSC73XX_ICPU_CTRL_EXT_ACC_EN)
126
127#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \
128                 VSC73XX_ICPU_CTRL_BOOT_EN | \
129                 VSC73XX_ICPU_CTRL_CLK_EN | \
130                 VSC73XX_ICPU_CTRL_SRST)
131
132#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \
133                 VSC73XX_ADVPORTM_EXC_COL_CONT | \
134                 VSC73XX_ADVPORTM_EXT_PORT | \
135                 VSC73XX_ADVPORTM_INV_GTX | \
136                 VSC73XX_ADVPORTM_ENA_GTX | \
137                 VSC73XX_ADVPORTM_DDR_MODE | \
138                 VSC73XX_ADVPORTM_IO_LOOPBACK | \
139                 VSC73XX_ADVPORTM_HOST_LOOPBACK)
140
141#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \
142                 VSC73XX_ADVPORTM_ENA_GTX | \
143                 VSC73XX_ADVPORTM_DDR_MODE)
144
145#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \
146                 VSC73XX_MAC_CFG_MAC_RX_RST | \
147                 VSC73XX_MAC_CFG_MAC_TX_RST)
148
149#define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \
150                 VSC73XX_MAC_CFG_FDX | \
151                 VSC73XX_MAC_CFG_GIGE | \
152                 VSC73XX_MAC_CFG_RX_EN)
153
154#define VSC73XX_RESET_DELAY 100
155
156struct vsc7385 {
157    struct spi_device *spi;
158    struct mutex lock;
159    struct vsc7385_platform_data *pdata;
160};
161
162static int vsc7385_is_addr_valid(u8 block, u8 subblock)
163{
164    switch (block) {
165    case VSC73XX_BLOCK_MAC:
166        switch (subblock) {
167        case 0 ... 4:
168        case 6:
169            return 1;
170        }
171        break;
172
173    case VSC73XX_BLOCK_2:
174    case VSC73XX_BLOCK_SYSTEM:
175        switch (subblock) {
176        case 0:
177            return 1;
178        }
179        break;
180
181    case VSC73XX_BLOCK_MII:
182    case VSC73XX_BLOCK_4:
183    case VSC73XX_BLOCK_5:
184        switch (subblock) {
185        case 0 ... 1:
186            return 1;
187        }
188        break;
189    }
190
191    return 0;
192}
193
194static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock)
195{
196    u8 ret;
197
198    ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT;
199    ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT;
200    ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK;
201
202    return ret;
203}
204
205static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg,
206            u32 *value)
207{
208    u8 cmd[4];
209    u8 buf[4];
210    struct spi_transfer t[2];
211    struct spi_message m;
212    int err;
213
214    if (!vsc7385_is_addr_valid(block, subblock))
215        return -EINVAL;
216
217    spi_message_init(&m);
218
219    memset(&t, 0, sizeof(t));
220
221    t[0].tx_buf = cmd;
222    t[0].len = sizeof(cmd);
223    spi_message_add_tail(&t[0], &m);
224
225    t[1].rx_buf = buf;
226    t[1].len = sizeof(buf);
227    spi_message_add_tail(&t[1], &m);
228
229    cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock);
230    cmd[1] = reg;
231    cmd[2] = 0;
232    cmd[3] = 0;
233
234    mutex_lock(&vsc->lock);
235    err = spi_sync(vsc->spi, &m);
236    mutex_unlock(&vsc->lock);
237
238    if (err)
239        return err;
240
241    *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) |
242         (((u32) buf[2]) << 8) | ((u32) buf[3]);
243
244    return 0;
245}
246
247
248static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg,
249             u32 value)
250{
251    u8 cmd[2];
252    u8 buf[4];
253    struct spi_transfer t[2];
254    struct spi_message m;
255    int err;
256
257    if (!vsc7385_is_addr_valid(block, subblock))
258        return -EINVAL;
259
260    spi_message_init(&m);
261
262    memset(&t, 0, sizeof(t));
263
264    t[0].tx_buf = cmd;
265    t[0].len = sizeof(cmd);
266    spi_message_add_tail(&t[0], &m);
267
268    t[1].tx_buf = buf;
269    t[1].len = sizeof(buf);
270    spi_message_add_tail(&t[1], &m);
271
272    cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock);
273    cmd[1] = reg;
274
275    buf[0] = (value >> 24) & 0xff;
276    buf[1] = (value >> 16) & 0xff;
277    buf[2] = (value >> 8) & 0xff;
278    buf[3] = value & 0xff;
279
280    mutex_lock(&vsc->lock);
281    err = spi_sync(vsc->spi, &m);
282    mutex_unlock(&vsc->lock);
283
284    return err;
285}
286
287static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block,
288                       u8 subblock, u8 reg, u32 value,
289                       u32 read_mask, u32 read_val)
290{
291    struct spi_device *spi = vsc->spi;
292    u32 t;
293    int err;
294
295    err = vsc7385_write(vsc, block, subblock, reg, value);
296    if (err)
297        return err;
298
299    err = vsc7385_read(vsc, block, subblock, reg, &t);
300    if (err)
301        return err;
302
303    if ((t & read_mask) != read_val) {
304        dev_err(&spi->dev, "register write error\n");
305        return -EIO;
306    }
307
308    return 0;
309}
310
311static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val)
312{
313    return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0,
314                 VSC73XX_ICPU_CLOCK_DELAY, val);
315}
316
317static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val)
318{
319    return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
320                VSC73XX_ICPU_CLOCK_DELAY, val);
321}
322
323static inline int vsc7385_icpu_stop(struct vsc7385 *vsc)
324{
325    return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL,
326                 VSC73XX_ICPU_CTRL_STOP);
327}
328
329static inline int vsc7385_icpu_start(struct vsc7385 *vsc)
330{
331    return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL,
332                 VSC73XX_ICPU_CTRL_START);
333}
334
335static inline int vsc7385_icpu_reset(struct vsc7385 *vsc)
336{
337    int rc;
338
339    rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR,
340               0x0000);
341    if (rc)
342        dev_err(&vsc->spi->dev,
343            "could not reset microcode, err=%d\n", rc);
344
345    return rc;
346}
347
348static int vsc7385_upload_ucode(struct vsc7385 *vsc)
349{
350    struct spi_device *spi = vsc->spi;
351    const struct firmware *firmware;
352    char *ucode_name;
353    unsigned char *dp;
354    unsigned int curVal;
355    int i;
356    int diffs;
357    int rc;
358
359    ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name
360                          : "vsc7385_ucode.bin";
361    rc = request_firmware(&firmware, ucode_name, &spi->dev);
362    if (rc) {
363        dev_err(&spi->dev, "request_firmware failed, err=%d\n",
364            rc);
365        return rc;
366    }
367
368    rc = vsc7385_icpu_stop(vsc);
369    if (rc)
370        goto out;
371
372    rc = vsc7385_icpu_reset(vsc);
373    if (rc)
374        goto out;
375
376    dev_info(&spi->dev, "uploading microcode...\n");
377
378    dp = (unsigned char *) firmware->data;
379    for (i = 0; i < firmware->size; i++) {
380        rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0,
381                   VSC73XX_ICPU_SRAM, *dp++);
382        if (rc) {
383            dev_err(&spi->dev, "could not load microcode, err=%d\n",
384                rc);
385            goto out;
386        }
387    }
388
389    rc = vsc7385_icpu_reset(vsc);
390    if (rc)
391        goto out;
392
393    dev_info(&spi->dev, "verifying microcode...\n");
394
395    dp = (unsigned char *) firmware->data;
396    diffs = 0;
397    for (i = 0; i < firmware->size; i++) {
398        rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
399                  VSC73XX_ICPU_SRAM, &curVal);
400        if (rc) {
401            dev_err(&spi->dev, "could not read microcode %d\n",rc);
402            goto out;
403        }
404
405        if (curVal > 0xff) {
406            dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n",
407                i, *dp, curVal);
408            rc = -EIO;
409            goto out;
410        }
411
412        if ((curVal & 0xff) != *dp) {
413            diffs++;
414            dev_err(&spi->dev, "verify error: %04x : %02x %02x\n",
415                i, *dp, curVal);
416
417            if (diffs > 4)
418                break;
419            }
420        dp++;
421    }
422
423    if (diffs) {
424        dev_err(&spi->dev, "microcode verification failed\n");
425        rc = -EIO;
426        goto out;
427    }
428
429    dev_info(&spi->dev, "microcode uploaded\n");
430
431    rc = vsc7385_icpu_start(vsc);
432
433 out:
434    release_firmware(firmware);
435    return rc;
436}
437
438static int vsc7385_setup(struct vsc7385 *vsc)
439{
440    struct vsc7385_platform_data *pdata = vsc->pdata;
441    u32 t;
442    int err;
443
444    err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0,
445                   VSC73XX_ICPU_CLOCK_DELAY,
446                   VSC7385_CLOCK_DELAY,
447                   VSC7385_CLOCK_DELAY_MASK,
448                   VSC7385_CLOCK_DELAY);
449    if (err)
450        goto err;
451
452    err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC,
453                   VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM,
454                   VSC7385_ADVPORTM_INIT,
455                   VSC7385_ADVPORTM_MASK,
456                   VSC7385_ADVPORTM_INIT);
457    if (err)
458        goto err;
459
460    err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC,
461                VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET);
462    if (err)
463        goto err;
464
465    t = VSC73XX_MAC_CFG_INIT;
466    t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg);
467    t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel);
468    if (pdata->mac_cfg.bit2)
469        t |= VSC73XX_MAC_CFG_BIT2;
470
471    err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC,
472                VSC73XX_MAC_CFG, t);
473    if (err)
474        goto err;
475
476    return 0;
477
478 err:
479    return err;
480}
481
482static int vsc7385_detect(struct vsc7385 *vsc)
483{
484    struct spi_device *spi = vsc->spi;
485    u32 t;
486    u32 id;
487    u32 rev;
488    int err;
489
490    err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
491                VSC73XX_ICPU_MBOX_VAL, &t);
492    if (err) {
493        dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err);
494        return err;
495    }
496
497    if (t == 0xffffffff) {
498        dev_dbg(&spi->dev, "assert chip reset\n");
499        if (vsc->pdata->reset)
500            vsc->pdata->reset();
501
502    }
503
504    err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
505                VSC73XX_ICPU_CHIPID, &t);
506    if (err) {
507        dev_err(&spi->dev, "unable to read chip id, err=%d\n", err);
508        return err;
509    }
510
511    id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK;
512    switch (id) {
513    case VSC73XX_ICPU_CHIPID_ID_7385:
514    case VSC73XX_ICPU_CHIPID_ID_7395:
515        break;
516    default:
517        dev_err(&spi->dev, "unsupported chip, id=%04x\n", id);
518        return -ENODEV;
519    }
520
521    rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) &
522          VSC73XX_ICPU_CHIPID_REV_MASK;
523    dev_info(&spi->dev, "VSC%04X (rev. %d) switch found \n", id, rev);
524
525    return 0;
526}
527
528static int __devinit vsc7385_probe(struct spi_device *spi)
529{
530    struct vsc7385 *vsc;
531    struct vsc7385_platform_data *pdata;
532    int err;
533
534    printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n");
535
536    pdata = spi->dev.platform_data;
537    if (!pdata) {
538        dev_err(&spi->dev, "no platform data specified\n");
539        return-ENODEV;
540    }
541
542    vsc = kzalloc(sizeof(*vsc), GFP_KERNEL);
543    if (!vsc) {
544        dev_err(&spi->dev, "no memory for private data\n");
545        return-ENOMEM;
546    }
547
548    mutex_init(&vsc->lock);
549    vsc->pdata = pdata;
550    vsc->spi = spi_dev_get(spi);
551    dev_set_drvdata(&spi->dev, vsc);
552
553    spi->mode = SPI_MODE_0;
554    spi->bits_per_word = 8;
555    err = spi_setup(spi);
556    if (err) {
557        dev_err(&spi->dev, "spi_setup failed, err=%d \n", err);
558        goto err_drvdata;
559    }
560
561    err = vsc7385_detect(vsc);
562    if (err) {
563        dev_err(&spi->dev, "no chip found, err=%d \n", err);
564        goto err_drvdata;
565    }
566
567    err = vsc7385_upload_ucode(vsc);
568    if (err)
569        goto err_drvdata;
570
571    err = vsc7385_setup(vsc);
572    if (err)
573        goto err_drvdata;
574
575    return 0;
576
577 err_drvdata:
578    dev_set_drvdata(&spi->dev, NULL);
579    kfree(vsc);
580    return err;
581}
582
583static int __devexit vsc7385_remove(struct spi_device *spi)
584{
585    struct vsc7385_data *vsc;
586
587    vsc = dev_get_drvdata(&spi->dev);
588    dev_set_drvdata(&spi->dev, NULL);
589    kfree(vsc);
590
591    return 0;
592}
593
594static struct spi_driver vsc7385_driver = {
595    .driver = {
596        .name = DRV_NAME,
597        .bus = &spi_bus_type,
598        .owner = THIS_MODULE,
599    },
600    .probe = vsc7385_probe,
601    .remove = __devexit_p(vsc7385_remove),
602};
603
604static int __init vsc7385_init(void)
605{
606    return spi_register_driver(&vsc7385_driver);
607}
608module_init(vsc7385_init);
609
610static void __exit vsc7385_exit(void)
611{
612    spi_unregister_driver(&vsc7385_driver);
613}
614module_exit(vsc7385_exit);
615
616MODULE_DESCRIPTION(DRV_DESC);
617MODULE_VERSION(DRV_VERSION);
618MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
619MODULE_LICENSE("GPL v2");
620
621

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