| 1 | /* |
| 2 | * HND SiliconBackplane MIPS core software interface. |
| 3 | * |
| 4 | * Copyright 2007, Broadcom Corporation |
| 5 | * All Rights Reserved. |
| 6 | * |
| 7 | * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY |
| 8 | * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM |
| 9 | * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS |
| 10 | * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef _hndmips_h_ |
| 15 | #define _hndmips_h_ |
| 16 | |
| 17 | extern void sb_mips_init(sb_t *sbh, uint shirq_map_base); |
| 18 | extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock); |
| 19 | extern void enable_pfc(uint32 mode); |
| 20 | extern uint32 sb_memc_get_ncdl(sb_t *sbh); |
| 21 | |
| 22 | #if defined(BCMPERFSTATS) |
| 23 | /* enable counting - exclusive version. Only one set of counters allowed at a time */ |
| 24 | extern void hndmips_perf_cyclecount_enable(void); |
| 25 | extern void hndmips_perf_instrcount_enable(void); |
| 26 | extern void hndmips_perf_icachecount_enable(void); |
| 27 | extern void hndmips_perf_dcachecount_enable(void); |
| 28 | /* start and stop counting */ |
| 29 | #define hndmips_perf_start01() \ |
| 30 | MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000) |
| 31 | #define hndmips_perf_stop01() \ |
| 32 | MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000) |
| 33 | /* retrieve coutners - counters *decrement* */ |
| 34 | #define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0)) |
| 35 | #define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1)) |
| 36 | #define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2)) |
| 37 | /* enable counting - modular version. Each counters can be enabled separately. */ |
| 38 | extern void hndmips_perf_icache_hit_enable(void); |
| 39 | extern void hndmips_perf_icache_miss_enable(void); |
| 40 | extern uint32 hndmips_perf_read_instrcount(void); |
| 41 | extern uint32 hndmips_perf_read_cache_miss(void); |
| 42 | extern uint32 hndmips_perf_read_cache_hit(void); |
| 43 | #endif |
| 44 | |
| 45 | #endif /* _hndmips_h_ */ |
| 46 | |
