| 1 | /* |
| 2 | * Broadcom SiliconBackplane hardware register definitions. |
| 3 | * |
| 4 | * Copyright 2007, Broadcom Corporation |
| 5 | * All Rights Reserved. |
| 6 | * |
| 7 | * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY |
| 8 | * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM |
| 9 | * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS |
| 10 | * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef _SBCONFIG_H |
| 15 | #define _SBCONFIG_H |
| 16 | #include "linuxver.h" |
| 17 | |
| 18 | /* cpp contortions to concatenate w/arg prescan */ |
| 19 | #ifndef PAD |
| 20 | #define _PADLINE(line) pad ## line |
| 21 | #define _XSTR(line) _PADLINE(line) |
| 22 | #define PAD _XSTR(__LINE__) |
| 23 | #endif |
| 24 | |
| 25 | /* |
| 26 | * SiliconBackplane Address Map. |
| 27 | * All regions may not exist on all chips. |
| 28 | */ |
| 29 | #define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */ |
| 30 | #define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ |
| 31 | #define SB_PCI_MEM_SZ (64 * 1024 * 1024) |
| 32 | #define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ |
| 33 | #define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ |
| 34 | #define SB_ENUM_BASE 0x18000000 /* Enumeration space base */ |
| 35 | #define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */ |
| 36 | |
| 37 | #define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ |
| 38 | #define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ |
| 39 | #define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */ |
| 40 | #define SB_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ |
| 41 | #define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ |
| 42 | #define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ |
| 43 | #define SB_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ |
| 44 | #define SB_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ |
| 45 | #define SB_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ |
| 46 | #define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ |
| 47 | #define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ |
| 48 | |
| 49 | #define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ |
| 50 | #define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ |
| 51 | #define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 |
| 52 | * (2 ZettaBytes), low 32 bits |
| 53 | */ |
| 54 | #define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 |
| 55 | * (2 ZettaBytes), high 32 bits |
| 56 | */ |
| 57 | #define SB_EUART (SB_EXTIF_BASE + 0x00800000) |
| 58 | #define SB_LED (SB_EXTIF_BASE + 0x00900000) |
| 59 | |
| 60 | |
| 61 | /* enumeration space related defs */ |
| 62 | #define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ |
| 63 | #define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE) |
| 64 | #define SB_MAXFUNCS 4 /* max. # functions per core */ |
| 65 | #define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */ |
| 66 | #define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */ |
| 67 | |
| 68 | /* mips address */ |
| 69 | #define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */ |
| 70 | |
| 71 | /* |
| 72 | * Sonics Configuration Space Registers. |
| 73 | */ |
| 74 | #define SBIPSFLAG 0x08 |
| 75 | #define SBTPSFLAG 0x18 |
| 76 | #define SBTMERRLOGA 0x48 /* sonics >= 2.3 */ |
| 77 | #define SBTMERRLOG 0x50 /* sonics >= 2.3 */ |
| 78 | #define SBADMATCH3 0x60 |
| 79 | #define SBADMATCH2 0x68 |
| 80 | #define SBADMATCH1 0x70 |
| 81 | #define SBIMSTATE 0x90 |
| 82 | #define SBINTVEC 0x94 |
| 83 | #define SBTMSTATELOW 0x98 |
| 84 | #define SBTMSTATEHIGH 0x9c |
| 85 | #define SBBWA0 0xa0 |
| 86 | #define SBIMCONFIGLOW 0xa8 |
| 87 | #define SBIMCONFIGHIGH 0xac |
| 88 | #define SBADMATCH0 0xb0 |
| 89 | #define SBTMCONFIGLOW 0xb8 |
| 90 | #define SBTMCONFIGHIGH 0xbc |
| 91 | #define SBBCONFIG 0xc0 |
| 92 | #define SBBSTATE 0xc8 |
| 93 | #define SBACTCNFG 0xd8 |
| 94 | #define SBFLAGST 0xe8 |
| 95 | #define SBIDLOW 0xf8 |
| 96 | #define SBIDHIGH 0xfc |
| 97 | |
| 98 | /* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have |
| 99 | * a few registers *below* that line. I think it would be very confusing to try |
| 100 | * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here, |
| 101 | */ |
| 102 | |
| 103 | #define SBIMERRLOGA 0xea8 |
| 104 | #define SBIMERRLOG 0xeb0 |
| 105 | #define SBTMPORTCONNID0 0xed8 |
| 106 | #define SBTMPORTLOCK0 0xef8 |
| 107 | |
| 108 | #ifndef _LANGUAGE_ASSEMBLY |
| 109 | |
| 110 | typedef volatile struct _sbconfig { |
| 111 | uint32 PAD[2]; |
| 112 | uint32 sbipsflag; /* initiator port ocp slave flag */ |
| 113 | uint32 PAD[3]; |
| 114 | uint32 sbtpsflag; /* target port ocp slave flag */ |
| 115 | uint32 PAD[11]; |
| 116 | uint32 sbtmerrloga; /* (sonics >= 2.3) */ |
| 117 | uint32 PAD; |
| 118 | uint32 sbtmerrlog; /* (sonics >= 2.3) */ |
| 119 | uint32 PAD[3]; |
| 120 | uint32 sbadmatch3; /* address match3 */ |
| 121 | uint32 PAD; |
| 122 | uint32 sbadmatch2; /* address match2 */ |
| 123 | uint32 PAD; |
| 124 | uint32 sbadmatch1; /* address match1 */ |
| 125 | uint32 PAD[7]; |
| 126 | uint32 sbimstate; /* initiator agent state */ |
| 127 | uint32 sbintvec; /* interrupt mask */ |
| 128 | uint32 sbtmstatelow; /* target state */ |
| 129 | uint32 sbtmstatehigh; /* target state */ |
| 130 | uint32 sbbwa0; /* bandwidth allocation table0 */ |
| 131 | uint32 PAD; |
| 132 | uint32 sbimconfiglow; /* initiator configuration */ |
| 133 | uint32 sbimconfighigh; /* initiator configuration */ |
| 134 | uint32 sbadmatch0; /* address match0 */ |
| 135 | uint32 PAD; |
| 136 | uint32 sbtmconfiglow; /* target configuration */ |
| 137 | uint32 sbtmconfighigh; /* target configuration */ |
| 138 | uint32 sbbconfig; /* broadcast configuration */ |
| 139 | uint32 PAD; |
| 140 | uint32 sbbstate; /* broadcast state */ |
| 141 | uint32 PAD[3]; |
| 142 | uint32 sbactcnfg; /* activate configuration */ |
| 143 | uint32 PAD[3]; |
| 144 | uint32 sbflagst; /* current sbflags */ |
| 145 | uint32 PAD[3]; |
| 146 | uint32 sbidlow; /* identification */ |
| 147 | uint32 sbidhigh; /* identification */ |
| 148 | } sbconfig_t; |
| 149 | |
| 150 | #endif /* _LANGUAGE_ASSEMBLY */ |
| 151 | |
| 152 | /* sbipsflag */ |
| 153 | #define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */ |
| 154 | #define SBIPS_INT1_SHIFT 0 |
| 155 | #define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */ |
| 156 | #define SBIPS_INT2_SHIFT 8 |
| 157 | #define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */ |
| 158 | #define SBIPS_INT3_SHIFT 16 |
| 159 | #define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */ |
| 160 | #define SBIPS_INT4_SHIFT 24 |
| 161 | |
| 162 | /* sbtpsflag */ |
| 163 | #define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */ |
| 164 | #define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */ |
| 165 | |
| 166 | /* sbtmerrlog */ |
| 167 | #define SBTMEL_CM 0x00000007 /* command */ |
| 168 | #define SBTMEL_CI 0x0000ff00 /* connection id */ |
| 169 | #define SBTMEL_EC 0x0f000000 /* error code */ |
| 170 | #define SBTMEL_ME 0x80000000 /* multiple error */ |
| 171 | |
| 172 | /* sbimstate */ |
| 173 | #define SBIM_PC 0xf /* pipecount */ |
| 174 | #define SBIM_AP_MASK 0x30 /* arbitration policy */ |
| 175 | #define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */ |
| 176 | #define SBIM_AP_TS 0x10 /* use timesliaces only */ |
| 177 | #define SBIM_AP_TK 0x20 /* use token only */ |
| 178 | #define SBIM_AP_RSV 0x30 /* reserved */ |
| 179 | #define SBIM_IBE 0x20000 /* inbanderror */ |
| 180 | #define SBIM_TO 0x40000 /* timeout */ |
| 181 | #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */ |
| 182 | #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */ |
| 183 | |
| 184 | /* sbtmstatelow */ |
| 185 | #define SBTML_RESET 0x1 /* reset */ |
| 186 | #define SBTML_REJ_MASK 0x6 /* reject */ |
| 187 | #define SBTML_REJ_SHIFT 1 |
| 188 | #define SBTML_CLK 0x10000 /* clock enable */ |
| 189 | #define SBTML_FGC 0x20000 /* force gated clocks on */ |
| 190 | #define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */ |
| 191 | #define SBTML_PE 0x40000000 /* pme enable */ |
| 192 | #define SBTML_BE 0x80000000 /* bist enable */ |
| 193 | |
| 194 | /* sbtmstatehigh */ |
| 195 | #define SBTMH_SERR 0x1 /* serror */ |
| 196 | #define SBTMH_INT 0x2 /* interrupt */ |
| 197 | #define SBTMH_BUSY 0x4 /* busy */ |
| 198 | #define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */ |
| 199 | #define SBTMH_FL_MASK 0x0fff0000 /* core-specific flags */ |
| 200 | #define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */ |
| 201 | #define SBTMH_GCR 0x20000000 /* gated clock request */ |
| 202 | #define SBTMH_BISTF 0x40000000 /* bist failed */ |
| 203 | #define SBTMH_BISTD 0x80000000 /* bist done */ |
| 204 | |
| 205 | |
| 206 | /* sbbwa0 */ |
| 207 | #define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */ |
| 208 | #define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */ |
| 209 | #define SBBWA_TAB1_SHIFT 16 |
| 210 | |
| 211 | /* sbimconfiglow */ |
| 212 | #define SBIMCL_STO_MASK 0x7 /* service timeout */ |
| 213 | #define SBIMCL_RTO_MASK 0x70 /* request timeout */ |
| 214 | #define SBIMCL_RTO_SHIFT 4 |
| 215 | #define SBIMCL_CID_MASK 0xff0000 /* connection id */ |
| 216 | #define SBIMCL_CID_SHIFT 16 |
| 217 | |
| 218 | /* sbimconfighigh */ |
| 219 | #define SBIMCH_IEM_MASK 0xc /* inband error mode */ |
| 220 | #define SBIMCH_TEM_MASK 0x30 /* timeout error mode */ |
| 221 | #define SBIMCH_TEM_SHIFT 4 |
| 222 | #define SBIMCH_BEM_MASK 0xc0 /* bus error mode */ |
| 223 | #define SBIMCH_BEM_SHIFT 6 |
| 224 | |
| 225 | /* sbadmatch0 */ |
| 226 | #define SBAM_TYPE_MASK 0x3 /* address type */ |
| 227 | #define SBAM_AD64 0x4 /* reserved */ |
| 228 | #define SBAM_ADINT0_MASK 0xf8 /* type0 size */ |
| 229 | #define SBAM_ADINT0_SHIFT 3 |
| 230 | #define SBAM_ADINT1_MASK 0x1f8 /* type1 size */ |
| 231 | #define SBAM_ADINT1_SHIFT 3 |
| 232 | #define SBAM_ADINT2_MASK 0x1f8 /* type2 size */ |
| 233 | #define SBAM_ADINT2_SHIFT 3 |
| 234 | #define SBAM_ADEN 0x400 /* enable */ |
| 235 | #define SBAM_ADNEG 0x800 /* negative decode */ |
| 236 | #define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */ |
| 237 | #define SBAM_BASE0_SHIFT 8 |
| 238 | #define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */ |
| 239 | #define SBAM_BASE1_SHIFT 12 |
| 240 | #define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */ |
| 241 | #define SBAM_BASE2_SHIFT 16 |
| 242 | |
| 243 | /* sbtmconfiglow */ |
| 244 | #define SBTMCL_CD_MASK 0xff /* clock divide */ |
| 245 | #define SBTMCL_CO_MASK 0xf800 /* clock offset */ |
| 246 | #define SBTMCL_CO_SHIFT 11 |
| 247 | #define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */ |
| 248 | #define SBTMCL_IF_SHIFT 18 |
| 249 | #define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */ |
| 250 | #define SBTMCL_IM_SHIFT 24 |
| 251 | |
| 252 | /* sbtmconfighigh */ |
| 253 | #define SBTMCH_BM_MASK 0x3 /* busy mode */ |
| 254 | #define SBTMCH_RM_MASK 0x3 /* retry mode */ |
| 255 | #define SBTMCH_RM_SHIFT 2 |
| 256 | #define SBTMCH_SM_MASK 0x30 /* stop mode */ |
| 257 | #define SBTMCH_SM_SHIFT 4 |
| 258 | #define SBTMCH_EM_MASK 0x300 /* sb error mode */ |
| 259 | #define SBTMCH_EM_SHIFT 8 |
| 260 | #define SBTMCH_IM_MASK 0xc00 /* int mode */ |
| 261 | #define SBTMCH_IM_SHIFT 10 |
| 262 | |
| 263 | /* sbbconfig */ |
| 264 | #define SBBC_LAT_MASK 0x3 /* sb latency */ |
| 265 | #define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */ |
| 266 | #define SBBC_MAX0_SHIFT 16 |
| 267 | #define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */ |
| 268 | #define SBBC_MAX1_SHIFT 20 |
| 269 | |
| 270 | /* sbbstate */ |
| 271 | #define SBBS_SRD 0x1 /* st reg disable */ |
| 272 | #define SBBS_HRD 0x2 /* hold reg disable */ |
| 273 | |
| 274 | /* sbidlow */ |
| 275 | #define SBIDL_CS_MASK 0x3 /* config space */ |
| 276 | #define SBIDL_AR_MASK 0x38 /* # address ranges supported */ |
| 277 | #define SBIDL_AR_SHIFT 3 |
| 278 | #define SBIDL_SYNCH 0x40 /* sync */ |
| 279 | #define SBIDL_INIT 0x80 /* initiator */ |
| 280 | #define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */ |
| 281 | #define SBIDL_MINLAT_SHIFT 8 |
| 282 | #define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */ |
| 283 | #define SBIDL_MAXLAT_SHIFT 12 |
| 284 | #define SBIDL_FIRST 0x10000 /* this initiator is first */ |
| 285 | #define SBIDL_CW_MASK 0xc0000 /* cycle counter width */ |
| 286 | #define SBIDL_CW_SHIFT 18 |
| 287 | #define SBIDL_TP_MASK 0xf00000 /* target ports */ |
| 288 | #define SBIDL_TP_SHIFT 20 |
| 289 | #define SBIDL_IP_MASK 0xf000000 /* initiator ports */ |
| 290 | #define SBIDL_IP_SHIFT 24 |
| 291 | #define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */ |
| 292 | #define SBIDL_RV_SHIFT 28 |
| 293 | #define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */ |
| 294 | #define SBIDL_RV_2_3 0x10000000 /* version 2.3 */ |
| 295 | |
| 296 | /* sbidhigh */ |
| 297 | #define SBIDH_RC_MASK 0x000f /* revision code */ |
| 298 | #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */ |
| 299 | #define SBIDH_RCE_SHIFT 8 |
| 300 | #define SBCOREREV(sbidh) \ |
| 301 | ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK)) |
| 302 | #define SBIDH_CC_MASK 0x8ff0 /* core code */ |
| 303 | #define SBIDH_CC_SHIFT 4 |
| 304 | #define SBIDH_VC_MASK 0xffff0000 /* vendor code */ |
| 305 | #define SBIDH_VC_SHIFT 16 |
| 306 | |
| 307 | #define SB_COMMIT 0xfd8 /* update buffered registers value */ |
| 308 | |
| 309 | /* vendor codes */ |
| 310 | #define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */ |
| 311 | |
| 312 | /* core codes */ |
| 313 | #define SB_NODEV 0x700 /* Invalid coreid */ |
| 314 | #define SB_CC 0x800 /* chipcommon core */ |
| 315 | #define SB_ILINE20 0x801 /* iline20 core */ |
| 316 | #define SB_SDRAM 0x803 /* sdram core */ |
| 317 | #define SB_PCI 0x804 /* pci core */ |
| 318 | #define SB_MIPS 0x805 /* mips core */ |
| 319 | #define SB_ENET 0x806 /* enet mac core */ |
| 320 | #define SB_CODEC 0x807 /* v90 codec core */ |
| 321 | #define SB_USB 0x808 /* usb 1.1 host/device core */ |
| 322 | #define SB_ADSL 0x809 /* ADSL core */ |
| 323 | #define SB_ILINE100 0x80a /* iline100 core */ |
| 324 | #define SB_IPSEC 0x80b /* ipsec core */ |
| 325 | #define SB_PCMCIA 0x80d /* pcmcia core */ |
| 326 | #define SB_SOCRAM 0x80e /* internal memory core */ |
| 327 | #define SB_MEMC 0x80f /* memc sdram core */ |
| 328 | #define SB_EXTIF 0x811 /* external interface core */ |
| 329 | #define SB_D11 0x812 /* 802.11 MAC core */ |
| 330 | #define SB_MIPS33 0x816 /* mips3302 core */ |
| 331 | #define SB_USB11H 0x817 /* usb 1.1 host core */ |
| 332 | #define SB_USB11D 0x818 /* usb 1.1 device core */ |
| 333 | #define SB_USB20H 0x819 /* usb 2.0 host core */ |
| 334 | #define SB_USB20D 0x81a /* usb 2.0 device core */ |
| 335 | #define SB_SDIOH 0x81b /* sdio host core */ |
| 336 | #define SB_ROBO 0x81c /* roboswitch core */ |
| 337 | #define SB_ATA100 0x81d /* parallel ATA core */ |
| 338 | #define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */ |
| 339 | #define SB_GIGETH 0x81f /* gigabit ethernet core */ |
| 340 | #define SB_PCIE 0x820 /* pci express core */ |
| 341 | #define SB_MIMO 0x821 /* MIMO phy core */ |
| 342 | #define SB_SRAMC 0x822 /* SRAM controller core */ |
| 343 | #define SB_MINIMAC 0x823 /* MINI MAC/phy core */ |
| 344 | #define SB_ARM7S 0x825 /* ARM7tdmi-s core */ |
| 345 | #define SB_SDIOD 0x829 /* SDIO device core */ |
| 346 | #define SB_ARMCM3 0x82a /* ARM Cortex M3 core */ |
| 347 | #define SB_OCP 0x830 /* OCP2OCP bridge core */ |
| 348 | #define SB_SC 0x831 /* shared common core */ |
| 349 | #define SB_AHB 0x832 /* OCP2AHB bridge core */ |
| 350 | |
| 351 | #define SB_CC_IDX 0 /* chipc, when present, is always core 0 */ |
| 352 | |
| 353 | /* Not an enumeration space register, but common to all cores to |
| 354 | * communicate w/PMU regarding Silicon Backplane clocking. |
| 355 | */ |
| 356 | #define SB_CLK_CTL_ST 0x1e0 /* clock control and status */ |
| 357 | |
| 358 | /* clk_ctl_st register */ |
| 359 | #define CCS_FORCEALP 0x00000001 /* force ALP request */ |
| 360 | #define CCS_FORCEHT 0x00000002 /* force HT request */ |
| 361 | #define CCS_FORCEILP 0x00000004 /* force ILP request */ |
| 362 | #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ |
| 363 | #define CCS_HTAREQ 0x00000010 /* HT Avail Request */ |
| 364 | #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ |
| 365 | #define CCS_ALPAVAIL 0x00010000 /* ALP is available */ |
| 366 | #define CCS_HTAVAIL 0x00020000 /* HT is available */ |
| 367 | #define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */ |
| 368 | #define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */ |
| 369 | |
| 370 | /* Not really related to Silicon Backplane, but a couple of software |
| 371 | * conventions for the use the flash space: |
| 372 | */ |
| 373 | |
| 374 | /* Minumum amount of flash we support */ |
| 375 | #define FLASH_MIN 0x00020000 /* Minimum flash size */ |
| 376 | |
| 377 | /* A boot/binary may have an embedded block that describes its size */ |
| 378 | #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */ |
| 379 | #define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ |
| 380 | #define BISZ_MAGIC_IDX 0 /* Word 0: magic */ |
| 381 | #define BISZ_TXTST_IDX 1 /* 1: text start */ |
| 382 | #define BISZ_TXTEND_IDX 2 /* 2: text end */ |
| 383 | #define BISZ_DATAST_IDX 3 /* 3: data start */ |
| 384 | #define BISZ_DATAEND_IDX 4 /* 4: data end */ |
| 385 | #define BISZ_BSSST_IDX 5 /* 5: bss start */ |
| 386 | #define BISZ_BSSEND_IDX 6 /* 6: bss end */ |
| 387 | #define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */ |
| 388 | |
| 389 | #endif /* _SBCONFIG_H */ |
| 390 | |
