| 1 | /* |
| 2 | * Hardware-specific External Interface I/O core definitions |
| 3 | * for the BCM47xx family of SiliconBackplane-based chips. |
| 4 | * |
| 5 | * The External Interface core supports a total of three external chip selects |
| 6 | * supporting external interfaces. One of the external chip selects is |
| 7 | * used for Flash, one is used for PCMCIA, and the other may be |
| 8 | * programmed to support either a synchronous interface or an |
| 9 | * asynchronous interface. The asynchronous interface can be used to |
| 10 | * support external devices such as UARTs and the BCM2019 Bluetooth |
| 11 | * baseband processor. |
| 12 | * The external interface core also contains 2 on-chip 16550 UARTs, clock |
| 13 | * frequency control, a watchdog interrupt timer, and a GPIO interface. |
| 14 | * |
| 15 | * Copyright 2006, Broadcom Corporation |
| 16 | * All Rights Reserved. |
| 17 | * |
| 18 | * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY |
| 19 | * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM |
| 20 | * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS |
| 21 | * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #ifndef _SBEXTIF_H |
| 26 | #define _SBEXTIF_H |
| 27 | |
| 28 | /* external interface address space */ |
| 29 | #define EXTIF_PCMCIA_MEMBASE(x) (x) |
| 30 | #define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000) |
| 31 | #define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000) |
| 32 | #define EXTIF_CFGIF_BASE(x) ((x) + 0x800000) |
| 33 | #define EXTIF_FLASH_BASE(x) ((x) + 0xc00000) |
| 34 | |
| 35 | /* cpp contortions to concatenate w/arg prescan */ |
| 36 | #ifndef PAD |
| 37 | #define _PADLINE(line) pad ## line |
| 38 | #define _XSTR(line) _PADLINE(line) |
| 39 | #define PAD _XSTR(__LINE__) |
| 40 | #endif /* PAD */ |
| 41 | |
| 42 | /* |
| 43 | * The multiple instances of output and output enable registers |
| 44 | * are present to allow driver software for multiple cores to control |
| 45 | * gpio outputs without needing to share a single register pair. |
| 46 | */ |
| 47 | struct gpiouser { |
| 48 | uint32 out; |
| 49 | uint32 outen; |
| 50 | }; |
| 51 | #define NGPIOUSER 5 |
| 52 | |
| 53 | typedef volatile struct { |
| 54 | uint32 corecontrol; |
| 55 | uint32 extstatus; |
| 56 | uint32 PAD[2]; |
| 57 | |
| 58 | /* pcmcia control registers */ |
| 59 | uint32 pcmcia_config; |
| 60 | uint32 pcmcia_memwait; |
| 61 | uint32 pcmcia_attrwait; |
| 62 | uint32 pcmcia_iowait; |
| 63 | |
| 64 | /* programmable interface control registers */ |
| 65 | uint32 prog_config; |
| 66 | uint32 prog_waitcount; |
| 67 | |
| 68 | /* flash control registers */ |
| 69 | uint32 flash_config; |
| 70 | uint32 flash_waitcount; |
| 71 | uint32 PAD[4]; |
| 72 | |
| 73 | uint32 watchdog; |
| 74 | |
| 75 | /* clock control */ |
| 76 | uint32 clockcontrol_n; |
| 77 | uint32 clockcontrol_sb; |
| 78 | uint32 clockcontrol_pci; |
| 79 | uint32 clockcontrol_mii; |
| 80 | uint32 PAD[3]; |
| 81 | |
| 82 | /* gpio */ |
| 83 | uint32 gpioin; |
| 84 | struct gpiouser gpio[NGPIOUSER]; |
| 85 | uint32 PAD; |
| 86 | uint32 ejtagouten; |
| 87 | uint32 gpiointpolarity; |
| 88 | uint32 gpiointmask; |
| 89 | uint32 PAD[153]; |
| 90 | |
| 91 | uint8 uartdata; |
| 92 | uint8 PAD[3]; |
| 93 | uint8 uartimer; |
| 94 | uint8 PAD[3]; |
| 95 | uint8 uartfcr; |
| 96 | uint8 PAD[3]; |
| 97 | uint8 uartlcr; |
| 98 | uint8 PAD[3]; |
| 99 | uint8 uartmcr; |
| 100 | uint8 PAD[3]; |
| 101 | uint8 uartlsr; |
| 102 | uint8 PAD[3]; |
| 103 | uint8 uartmsr; |
| 104 | uint8 PAD[3]; |
| 105 | uint8 uartscratch; |
| 106 | uint8 PAD[3]; |
| 107 | } extifregs_t; |
| 108 | |
| 109 | /* corecontrol */ |
| 110 | #define CC_UE (1 << 0) /* uart enable */ |
| 111 | |
| 112 | /* extstatus */ |
| 113 | #define ES_EM (1 << 0) /* endian mode (ro) */ |
| 114 | #define ES_EI (1 << 1) /* external interrupt pin (ro) */ |
| 115 | #define ES_GI (1 << 2) /* gpio interrupt pin (ro) */ |
| 116 | |
| 117 | /* gpio bit mask */ |
| 118 | #define GPIO_BIT0 (1 << 0) |
| 119 | #define GPIO_BIT1 (1 << 1) |
| 120 | #define GPIO_BIT2 (1 << 2) |
| 121 | #define GPIO_BIT3 (1 << 3) |
| 122 | #define GPIO_BIT4 (1 << 4) |
| 123 | #define GPIO_BIT5 (1 << 5) |
| 124 | #define GPIO_BIT6 (1 << 6) |
| 125 | #define GPIO_BIT7 (1 << 7) |
| 126 | |
| 127 | |
| 128 | /* pcmcia/prog/flash_config */ |
| 129 | #define CF_EN (1 << 0) /* enable */ |
| 130 | #define CF_EM_MASK 0xe /* mode */ |
| 131 | #define CF_EM_SHIFT 1 |
| 132 | #define CF_EM_FLASH 0x0 /* flash/asynchronous mode */ |
| 133 | #define CF_EM_SYNC 0x2 /* synchronous mode */ |
| 134 | #define CF_EM_PCMCIA 0x4 /* pcmcia mode */ |
| 135 | #define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */ |
| 136 | #define CF_BS (1 << 5) /* byteswap */ |
| 137 | #define CF_CD_MASK 0xc0 /* clock divider */ |
| 138 | #define CF_CD_SHIFT 6 |
| 139 | #define CF_CD_DIV2 0x0 /* backplane/2 */ |
| 140 | #define CF_CD_DIV3 0x40 /* backplane/3 */ |
| 141 | #define CF_CD_DIV4 0x80 /* backplane/4 */ |
| 142 | #define CF_CE (1 << 8) /* clock enable */ |
| 143 | #define CF_SB (1 << 9) /* size/bytestrobe (synch only) */ |
| 144 | |
| 145 | /* pcmcia_memwait */ |
| 146 | #define PM_W0_MASK 0x3f /* waitcount0 */ |
| 147 | #define PM_W1_MASK 0x1f00 /* waitcount1 */ |
| 148 | #define PM_W1_SHIFT 8 |
| 149 | #define PM_W2_MASK 0x1f0000 /* waitcount2 */ |
| 150 | #define PM_W2_SHIFT 16 |
| 151 | #define PM_W3_MASK 0x1f000000 /* waitcount3 */ |
| 152 | #define PM_W3_SHIFT 24 |
| 153 | |
| 154 | /* pcmcia_attrwait */ |
| 155 | #define PA_W0_MASK 0x3f /* waitcount0 */ |
| 156 | #define PA_W1_MASK 0x1f00 /* waitcount1 */ |
| 157 | #define PA_W1_SHIFT 8 |
| 158 | #define PA_W2_MASK 0x1f0000 /* waitcount2 */ |
| 159 | #define PA_W2_SHIFT 16 |
| 160 | #define PA_W3_MASK 0x1f000000 /* waitcount3 */ |
| 161 | #define PA_W3_SHIFT 24 |
| 162 | |
| 163 | /* prog_waitcount */ |
| 164 | #define PW_W0_MASK 0x0000001f /* waitcount0 */ |
| 165 | #define PW_W1_MASK 0x00001f00 /* waitcount1 */ |
| 166 | #define PW_W1_SHIFT 8 |
| 167 | #define PW_W2_MASK 0x001f0000 /* waitcount2 */ |
| 168 | #define PW_W2_SHIFT 16 |
| 169 | #define PW_W3_MASK 0x1f000000 /* waitcount3 */ |
| 170 | #define PW_W3_SHIFT 24 |
| 171 | |
| 172 | #define PW_W0 0x0000000c |
| 173 | #define PW_W1 0x00000a00 |
| 174 | #define PW_W2 0x00020000 |
| 175 | #define PW_W3 0x01000000 |
| 176 | |
| 177 | /* flash_waitcount */ |
| 178 | #define FW_W0_MASK 0x1f /* waitcount0 */ |
| 179 | #define FW_W1_MASK 0x1f00 /* waitcount1 */ |
| 180 | #define FW_W1_SHIFT 8 |
| 181 | #define FW_W2_MASK 0x1f0000 /* waitcount2 */ |
| 182 | #define FW_W2_SHIFT 16 |
| 183 | #define FW_W3_MASK 0x1f000000 /* waitcount3 */ |
| 184 | #define FW_W3_SHIFT 24 |
| 185 | |
| 186 | /* watchdog */ |
| 187 | #define WATCHDOG_CLOCK 48000000 /* Hz */ |
| 188 | |
| 189 | /* clockcontrol_n */ |
| 190 | #define CN_N1_MASK 0x3f /* n1 control */ |
| 191 | #define CN_N2_MASK 0x3f00 /* n2 control */ |
| 192 | #define CN_N2_SHIFT 8 |
| 193 | |
| 194 | /* clockcontrol_sb/pci/mii */ |
| 195 | #define CC_M1_MASK 0x3f /* m1 control */ |
| 196 | #define CC_M2_MASK 0x3f00 /* m2 control */ |
| 197 | #define CC_M2_SHIFT 8 |
| 198 | #define CC_M3_MASK 0x3f0000 /* m3 control */ |
| 199 | #define CC_M3_SHIFT 16 |
| 200 | #define CC_MC_MASK 0x1f000000 /* mux control */ |
| 201 | #define CC_MC_SHIFT 24 |
| 202 | |
| 203 | /* Clock control default values */ |
| 204 | #define CC_DEF_N 0x0009 /* Default values for bcm4710 */ |
| 205 | #define CC_DEF_100 0x04020011 |
| 206 | #define CC_DEF_33 0x11030011 |
| 207 | #define CC_DEF_25 0x11050011 |
| 208 | |
| 209 | /* Clock control values for 125Mhz */ |
| 210 | #define CC_125_N 0x0802 |
| 211 | #define CC_125_M 0x04020009 |
| 212 | #define CC_125_M25 0x11090009 |
| 213 | #define CC_125_M33 0x11090005 |
| 214 | |
| 215 | /* Clock control magic field values */ |
| 216 | #define CC_F6_2 0x02 /* A factor of 2 in */ |
| 217 | #define CC_F6_3 0x03 /* 6-bit fields like */ |
| 218 | #define CC_F6_4 0x05 /* N1, M1 or M3 */ |
| 219 | #define CC_F6_5 0x09 |
| 220 | #define CC_F6_6 0x11 |
| 221 | #define CC_F6_7 0x21 |
| 222 | |
| 223 | #define CC_F5_BIAS 5 /* 5-bit fields get this added */ |
| 224 | |
| 225 | #define CC_MC_BYPASS 0x08 |
| 226 | #define CC_MC_M1 0x04 |
| 227 | #define CC_MC_M1M2 0x02 |
| 228 | #define CC_MC_M1M2M3 0x01 |
| 229 | #define CC_MC_M1M3 0x11 |
| 230 | |
| 231 | #define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */ |
| 232 | |
| 233 | #endif /* _SBEXTIF_H */ |
| 234 | |
