| 1 | /* |
| 2 | * Broadcom SiliconBackplane MIPS definitions |
| 3 | * |
| 4 | * SB MIPS cores are custom MIPS32 processors with SiliconBackplane |
| 5 | * OCP interfaces. The CP0 processor ID is 0x00024000, where bits |
| 6 | * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP |
| 7 | * interface. The core revision is stored in the SB ID register in SB |
| 8 | * configuration space. |
| 9 | * |
| 10 | * Copyright 2007, Broadcom Corporation |
| 11 | * All Rights Reserved. |
| 12 | * |
| 13 | * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY |
| 14 | * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM |
| 15 | * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS |
| 16 | * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #ifndef _sbhndmips_h_ |
| 21 | #define _sbhndmips_h_ |
| 22 | |
| 23 | #include <mipsinc.h> |
| 24 | |
| 25 | #ifndef _LANGUAGE_ASSEMBLY |
| 26 | |
| 27 | /* cpp contortions to concatenate w/arg prescan */ |
| 28 | #ifndef PAD |
| 29 | #define _PADLINE(line) pad ## line |
| 30 | #define _XSTR(line) _PADLINE(line) |
| 31 | #define PAD _XSTR(__LINE__) |
| 32 | #endif /* PAD */ |
| 33 | |
| 34 | typedef volatile struct { |
| 35 | uint32 corecontrol; |
| 36 | uint32 PAD[2]; |
| 37 | uint32 biststatus; |
| 38 | uint32 PAD[4]; |
| 39 | uint32 intstatus; |
| 40 | uint32 intmask; |
| 41 | uint32 timer; |
| 42 | } mipsregs_t; |
| 43 | |
| 44 | #endif /* _LANGUAGE_ASSEMBLY */ |
| 45 | |
| 46 | #endif /* _sbhndmips_h_ */ |
| 47 | |
