| 1 | /* |
| 2 | * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions. |
| 3 | * |
| 4 | * Copyright 2007, Broadcom Corporation |
| 5 | * All Rights Reserved. |
| 6 | * |
| 7 | * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY |
| 8 | * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM |
| 9 | * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS |
| 10 | * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef _SBMEMC_H |
| 15 | #define _SBMEMC_H |
| 16 | |
| 17 | #ifdef _LANGUAGE_ASSEMBLY |
| 18 | |
| 19 | #define MEMC_CONTROL 0x00 |
| 20 | #define MEMC_CONFIG 0x04 |
| 21 | #define MEMC_REFRESH 0x08 |
| 22 | #define MEMC_BISTSTAT 0x0c |
| 23 | #define MEMC_MODEBUF 0x10 |
| 24 | #define MEMC_BKCLS 0x14 |
| 25 | #define MEMC_PRIORINV 0x18 |
| 26 | #define MEMC_DRAMTIM 0x1c |
| 27 | #define MEMC_INTSTAT 0x20 |
| 28 | #define MEMC_INTMASK 0x24 |
| 29 | #define MEMC_INTINFO 0x28 |
| 30 | #define MEMC_NCDLCTL 0x30 |
| 31 | #define MEMC_RDNCDLCOR 0x34 |
| 32 | #define MEMC_WRNCDLCOR 0x38 |
| 33 | #define MEMC_MISCDLYCTL 0x3c |
| 34 | #define MEMC_DQSGATENCDL 0x40 |
| 35 | #define MEMC_SPARE 0x44 |
| 36 | #define MEMC_TPADDR 0x48 |
| 37 | #define MEMC_TPDATA 0x4c |
| 38 | #define MEMC_BARRIER 0x50 |
| 39 | #define MEMC_CORE 0x54 |
| 40 | |
| 41 | #else /* !_LANGUAGE_ASSEMBLY */ |
| 42 | |
| 43 | /* Sonics side: MEMC core registers */ |
| 44 | typedef volatile struct sbmemcregs { |
| 45 | uint32 control; |
| 46 | uint32 config; |
| 47 | uint32 refresh; |
| 48 | uint32 biststat; |
| 49 | uint32 modebuf; |
| 50 | uint32 bkcls; |
| 51 | uint32 priorinv; |
| 52 | uint32 dramtim; |
| 53 | uint32 intstat; |
| 54 | uint32 intmask; |
| 55 | uint32 intinfo; |
| 56 | uint32 reserved1; |
| 57 | uint32 ncdlctl; |
| 58 | uint32 rdncdlcor; |
| 59 | uint32 wrncdlcor; |
| 60 | uint32 miscdlyctl; |
| 61 | uint32 dqsgatencdl; |
| 62 | uint32 spare; |
| 63 | uint32 tpaddr; |
| 64 | uint32 tpdata; |
| 65 | uint32 barrier; |
| 66 | uint32 core; |
| 67 | } sbmemcregs_t; |
| 68 | |
| 69 | #endif /* _LANGUAGE_ASSEMBLY */ |
| 70 | |
| 71 | /* MEMC Core Init values (OCP ID 0x80f) */ |
| 72 | |
| 73 | /* For sdr: */ |
| 74 | #define MEMC_SD_CONFIG_INIT 0x00048000 |
| 75 | #define MEMC_SD_DRAMTIM2_INIT 0x000754d8 |
| 76 | #define MEMC_SD_DRAMTIM3_INIT 0x000754da |
| 77 | #define MEMC_SD_RDNCDLCOR_INIT 0x00000000 |
| 78 | #define MEMC_SD_WRNCDLCOR_INIT 0x49351200 |
| 79 | #define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */ |
| 80 | #define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b |
| 81 | #define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */ |
| 82 | #define MEMC_SD_CONTROL_INIT0 0x00000002 |
| 83 | #define MEMC_SD_CONTROL_INIT1 0x00000008 |
| 84 | #define MEMC_SD_CONTROL_INIT2 0x00000004 |
| 85 | #define MEMC_SD_CONTROL_INIT3 0x00000010 |
| 86 | #define MEMC_SD_CONTROL_INIT4 0x00000001 |
| 87 | #define MEMC_SD_MODEBUF_INIT 0x00000000 |
| 88 | #define MEMC_SD_REFRESH_INIT 0x0000840f |
| 89 | |
| 90 | |
| 91 | /* This is for SDRM8X8X4 */ |
| 92 | #define MEMC_SDR_INIT 0x0008 |
| 93 | #define MEMC_SDR_MODE 0x32 |
| 94 | #define MEMC_SDR_NCDL 0x00020032 |
| 95 | #define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */ |
| 96 | |
| 97 | /* For ddr: */ |
| 98 | #define MEMC_CONFIG_INIT 0x00048000 |
| 99 | #define MEMC_DRAMTIM2_INIT 0x000754d8 |
| 100 | #define MEMC_DRAMTIM25_INIT 0x000754d9 |
| 101 | #define MEMC_RDNCDLCOR_INIT 0x00000000 |
| 102 | #define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */ |
| 103 | #define MEMC_WRNCDLCOR_INIT 0x49351200 |
| 104 | #define MEMC_1_WRNCDLCOR_INIT 0x14500200 |
| 105 | #define MEMC_DQSGATENCDL_INIT 0x00030000 |
| 106 | #define MEMC_MISCDLYCTL_INIT 0x21061c1b |
| 107 | #define MEMC_1_MISCDLYCTL_INIT 0x21021400 |
| 108 | #define MEMC_NCDLCTL_INIT 0x00002001 |
| 109 | #define MEMC_CONTROL_INIT0 0x00000002 |
| 110 | #define MEMC_CONTROL_INIT1 0x00000008 |
| 111 | #define MEMC_MODEBUF_INIT0 0x00004000 |
| 112 | #define MEMC_CONTROL_INIT2 0x00000010 |
| 113 | #define MEMC_MODEBUF_INIT1 0x00000100 |
| 114 | #define MEMC_CONTROL_INIT3 0x00000010 |
| 115 | #define MEMC_CONTROL_INIT4 0x00000008 |
| 116 | #define MEMC_REFRESH_INIT 0x0000840f |
| 117 | #define MEMC_CONTROL_INIT5 0x00000004 |
| 118 | #define MEMC_MODEBUF_INIT2 0x00000000 |
| 119 | #define MEMC_CONTROL_INIT6 0x00000010 |
| 120 | #define MEMC_CONTROL_INIT7 0x00000001 |
| 121 | |
| 122 | |
| 123 | /* This is for DDRM16X16X2 */ |
| 124 | #define MEMC_DDR_INIT 0x0009 |
| 125 | #define MEMC_DDR_MODE 0x62 |
| 126 | #define MEMC_DDR_NCDL 0x0005050a |
| 127 | #define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */ |
| 128 | |
| 129 | /* mask for sdr/ddr calibration registers */ |
| 130 | #define MEMC_RDNCDLCOR_RD_MASK 0x000000ff |
| 131 | #define MEMC_WRNCDLCOR_WR_MASK 0x000000ff |
| 132 | #define MEMC_DQSGATENCDL_G_MASK 0x000000ff |
| 133 | |
| 134 | /* masks for miscdlyctl registers */ |
| 135 | #define MEMC_MISC_SM_MASK 0x30000000 |
| 136 | #define MEMC_MISC_SM_SHIFT 28 |
| 137 | #define MEMC_MISC_SD_MASK 0x0f000000 |
| 138 | #define MEMC_MISC_SD_SHIFT 24 |
| 139 | |
| 140 | /* hw threshhold for calculating wr/rd for sdr memc */ |
| 141 | #define MEMC_CD_THRESHOLD 128 |
| 142 | |
| 143 | /* Low bit of init register says if memc is ddr or sdr */ |
| 144 | #define MEMC_CONFIG_DDR 0x00000001 |
| 145 | |
| 146 | #endif /* _SBMEMC_H */ |
| 147 | |
