| 1 | /* |
| 2 | * HND SiliconBackplane PCI core hardware definitions. |
| 3 | * |
| 4 | * Copyright 2007, Broadcom Corporation |
| 5 | * All Rights Reserved. |
| 6 | * |
| 7 | * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY |
| 8 | * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM |
| 9 | * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS |
| 10 | * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef _sbpci_h_ |
| 15 | #define _sbpci_h_ |
| 16 | |
| 17 | #ifndef _LANGUAGE_ASSEMBLY |
| 18 | |
| 19 | /* cpp contortions to concatenate w/arg prescan */ |
| 20 | #ifndef PAD |
| 21 | #define _PADLINE(line) pad ## line |
| 22 | #define _XSTR(line) _PADLINE(line) |
| 23 | #define PAD _XSTR(__LINE__) |
| 24 | #endif |
| 25 | |
| 26 | /* Sonics side: PCI core and host control registers */ |
| 27 | typedef struct sbpciregs { |
| 28 | uint32 control; /* PCI control */ |
| 29 | uint32 PAD[3]; |
| 30 | uint32 arbcontrol; /* PCI arbiter control */ |
| 31 | uint32 PAD[3]; |
| 32 | uint32 intstatus; /* Interrupt status */ |
| 33 | uint32 intmask; /* Interrupt mask */ |
| 34 | uint32 sbtopcimailbox; /* Sonics to PCI mailbox */ |
| 35 | uint32 PAD[9]; |
| 36 | uint32 bcastaddr; /* Sonics broadcast address */ |
| 37 | uint32 bcastdata; /* Sonics broadcast data */ |
| 38 | uint32 PAD[2]; |
| 39 | uint32 gpioin; /* ro: gpio input (>=rev2) */ |
| 40 | uint32 gpioout; /* rw: gpio output (>=rev2) */ |
| 41 | uint32 gpioouten; /* rw: gpio output enable (>= rev2) */ |
| 42 | uint32 gpiocontrol; /* rw: gpio control (>= rev2) */ |
| 43 | uint32 PAD[36]; |
| 44 | uint32 sbtopci0; /* Sonics to PCI translation 0 */ |
| 45 | uint32 sbtopci1; /* Sonics to PCI translation 1 */ |
| 46 | uint32 sbtopci2; /* Sonics to PCI translation 2 */ |
| 47 | uint32 PAD[189]; |
| 48 | uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */ |
| 49 | uint16 sprom[36]; /* SPROM shadow Area */ |
| 50 | uint32 PAD[46]; |
| 51 | } sbpciregs_t; |
| 52 | |
| 53 | #endif /* _LANGUAGE_ASSEMBLY */ |
| 54 | |
| 55 | /* PCI control */ |
| 56 | #define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ |
| 57 | #define PCI_RST 0x02 /* Value driven out to pin */ |
| 58 | #define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */ |
| 59 | #define PCI_CLK 0x08 /* Gate for clock driven out to pin */ |
| 60 | |
| 61 | /* PCI arbiter control */ |
| 62 | #define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */ |
| 63 | #define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */ |
| 64 | /* ParkID - for PCI corerev >= 8 */ |
| 65 | #define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */ |
| 66 | #define PCI_PARKID_SHIFT 2 |
| 67 | #define PCI_PARKID_EXT0 0 /* External master 0 */ |
| 68 | #define PCI_PARKID_EXT1 1 /* External master 1 */ |
| 69 | #define PCI_PARKID_EXT2 2 /* External master 2 */ |
| 70 | #define PCI_PARKID_EXT3 3 /* External master 3 (rev >= 11) */ |
| 71 | #define PCI_PARKID_INT 3 /* Internal master (rev < 11) */ |
| 72 | #define PCI11_PARKID_INT 4 /* Internal master (rev >= 11) */ |
| 73 | #define PCI_PARKID_LAST 4 /* Last active master (rev < 11) */ |
| 74 | #define PCI11_PARKID_LAST 5 /* Last active master (rev >= 11) */ |
| 75 | |
| 76 | /* Interrupt status/mask */ |
| 77 | #define PCI_INTA 0x01 /* PCI INTA# is asserted */ |
| 78 | #define PCI_INTB 0x02 /* PCI INTB# is asserted */ |
| 79 | #define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */ |
| 80 | #define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */ |
| 81 | #define PCI_PME 0x10 /* PCI PME# is asserted */ |
| 82 | |
| 83 | /* (General) PCI/SB mailbox interrupts, two bits per pci function */ |
| 84 | #define MAILBOX_F0_0 0x100 /* function 0, int 0 */ |
| 85 | #define MAILBOX_F0_1 0x200 /* function 0, int 1 */ |
| 86 | #define MAILBOX_F1_0 0x400 /* function 1, int 0 */ |
| 87 | #define MAILBOX_F1_1 0x800 /* function 1, int 1 */ |
| 88 | #define MAILBOX_F2_0 0x1000 /* function 2, int 0 */ |
| 89 | #define MAILBOX_F2_1 0x2000 /* function 2, int 1 */ |
| 90 | #define MAILBOX_F3_0 0x4000 /* function 3, int 0 */ |
| 91 | #define MAILBOX_F3_1 0x8000 /* function 3, int 1 */ |
| 92 | |
| 93 | /* Sonics broadcast address */ |
| 94 | #define BCAST_ADDR_MASK 0xff /* Broadcast register address */ |
| 95 | |
| 96 | /* Sonics to PCI translation types */ |
| 97 | #define SBTOPCI0_MASK 0xfc000000 |
| 98 | #define SBTOPCI1_MASK 0xfc000000 |
| 99 | #define SBTOPCI2_MASK 0xc0000000 |
| 100 | #define SBTOPCI_MEM 0 |
| 101 | #define SBTOPCI_IO 1 |
| 102 | #define SBTOPCI_CFG0 2 |
| 103 | #define SBTOPCI_CFG1 3 |
| 104 | #define SBTOPCI_PREF 0x4 /* prefetch enable */ |
| 105 | #define SBTOPCI_BURST 0x8 /* burst enable */ |
| 106 | #define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */ |
| 107 | #define SBTOPCI_RC_READ 0x00 /* memory read */ |
| 108 | #define SBTOPCI_RC_READLINE 0x10 /* memory read line */ |
| 109 | #define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */ |
| 110 | |
| 111 | /* PCI core index in SROM shadow area */ |
| 112 | #define SRSH_PI_OFFSET 0 /* first word */ |
| 113 | #define SRSH_PI_MASK 0xf000 /* bit 15:12 */ |
| 114 | #define SRSH_PI_SHIFT 12 /* bit 15:12 */ |
| 115 | |
| 116 | #endif /* _sbpci_h_ */ |
| 117 | |
