| 1 | /* |
| 2 | * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions. |
| 3 | * |
| 4 | * Copyright 2007, Broadcom Corporation |
| 5 | * All Rights Reserved. |
| 6 | * |
| 7 | * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY |
| 8 | * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM |
| 9 | * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS |
| 10 | * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef _SBPCMCIA_H |
| 15 | #define _SBPCMCIA_H |
| 16 | |
| 17 | |
| 18 | /* All the addresses that are offsets in attribute space are divided |
| 19 | * by two to account for the fact that odd bytes are invalid in |
| 20 | * attribute space and our read/write routines make the space appear |
| 21 | * as if they didn't exist. Still we want to show the original numbers |
| 22 | * as documented in the hnd_pcmcia core manual. |
| 23 | */ |
| 24 | |
| 25 | /* PCMCIA Function Configuration Registers */ |
| 26 | #define PCMCIA_FCR (0x700 / 2) |
| 27 | |
| 28 | #define FCR0_OFF 0 |
| 29 | #define FCR1_OFF (0x40 / 2) |
| 30 | #define FCR2_OFF (0x80 / 2) |
| 31 | #define FCR3_OFF (0xc0 / 2) |
| 32 | |
| 33 | #define PCMCIA_FCR0 (0x700 / 2) |
| 34 | #define PCMCIA_FCR1 (0x740 / 2) |
| 35 | #define PCMCIA_FCR2 (0x780 / 2) |
| 36 | #define PCMCIA_FCR3 (0x7c0 / 2) |
| 37 | |
| 38 | /* Standard PCMCIA FCR registers */ |
| 39 | |
| 40 | #define PCMCIA_COR 0 |
| 41 | |
| 42 | #define COR_RST 0x80 |
| 43 | #define COR_LEV 0x40 |
| 44 | #define COR_IRQEN 0x04 |
| 45 | #define COR_BLREN 0x01 |
| 46 | #define COR_FUNEN 0x01 |
| 47 | |
| 48 | |
| 49 | #define PCICIA_FCSR (2 / 2) |
| 50 | #define PCICIA_PRR (4 / 2) |
| 51 | #define PCICIA_SCR (6 / 2) |
| 52 | #define PCICIA_ESR (8 / 2) |
| 53 | |
| 54 | |
| 55 | #define PCM_MEMOFF 0x0000 |
| 56 | #define F0_MEMOFF 0x1000 |
| 57 | #define F1_MEMOFF 0x2000 |
| 58 | #define F2_MEMOFF 0x3000 |
| 59 | #define F3_MEMOFF 0x4000 |
| 60 | |
| 61 | /* Memory base in the function fcr's */ |
| 62 | #define MEM_ADDR0 (0x728 / 2) |
| 63 | #define MEM_ADDR1 (0x72a / 2) |
| 64 | #define MEM_ADDR2 (0x72c / 2) |
| 65 | |
| 66 | /* PCMCIA base plus Srom access in fcr0: */ |
| 67 | #define PCMCIA_ADDR0 (0x072e / 2) |
| 68 | #define PCMCIA_ADDR1 (0x0730 / 2) |
| 69 | #define PCMCIA_ADDR2 (0x0732 / 2) |
| 70 | |
| 71 | #define MEM_SEG (0x0734 / 2) |
| 72 | #define SROM_CS (0x0736 / 2) |
| 73 | #define SROM_DATAL (0x0738 / 2) |
| 74 | #define SROM_DATAH (0x073a / 2) |
| 75 | #define SROM_ADDRL (0x073c / 2) |
| 76 | #define SROM_ADDRH (0x073e / 2) |
| 77 | #define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */ |
| 78 | #define SROM_INFO (0x07be / 2) /* Corerev >= 6 */ |
| 79 | |
| 80 | /* Values for srom_cs: */ |
| 81 | #define SROM_IDLE 0 |
| 82 | #define SROM_WRITE 1 |
| 83 | #define SROM_READ 2 |
| 84 | #define SROM_WEN 4 |
| 85 | #define SROM_WDS 7 |
| 86 | #define SROM_DONE 8 |
| 87 | |
| 88 | /* Fields in srom_info: */ |
| 89 | #define SRI_SZ_MASK 0x03 |
| 90 | #define SRI_BLANK 0x04 |
| 91 | #define SRI_OTP 0x80 |
| 92 | |
| 93 | /* CIS stuff */ |
| 94 | |
| 95 | /* The CIS stops where the FCRs start */ |
| 96 | #define CIS_SIZE PCMCIA_FCR |
| 97 | |
| 98 | /* CIS tuple length field max */ |
| 99 | #define CIS_TUPLE_LEN_MAX 0xff |
| 100 | |
| 101 | /* Standard tuples we know about */ |
| 102 | |
| 103 | #define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */ |
| 104 | #define CISTPL_MANFID 0x20 /* Manufacturer and device id */ |
| 105 | #define CISTPL_FUNCID 0x21 /* Function identification */ |
| 106 | #define CISTPL_FUNCE 0x22 /* Function extensions */ |
| 107 | #define CISTPL_CFTABLE 0x1b /* Config table entry */ |
| 108 | #define CISTPL_END 0xff /* End of the CIS tuple chain */ |
| 109 | |
| 110 | /* Function identifier provides context for the function extentions tuple */ |
| 111 | |
| 112 | |
| 113 | /* Function extensions for LANs */ |
| 114 | |
| 115 | #define LAN_TECH 1 /* Technology type */ |
| 116 | #define LAN_SPEED 2 /* Raw bit rate */ |
| 117 | #define LAN_MEDIA 3 /* Transmission media */ |
| 118 | #define LAN_NID 4 /* Node identification (aka MAC addr) */ |
| 119 | #define LAN_CONN 5 /* Connector standard */ |
| 120 | |
| 121 | |
| 122 | /* CFTable */ |
| 123 | #define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */ |
| 124 | #define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */ |
| 125 | #define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */ |
| 126 | |
| 127 | /* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll |
| 128 | * take one for HNBU, and use "extensions" (a la FUNCE) within it. |
| 129 | */ |
| 130 | |
| 131 | #define CISTPL_BRCM_HNBU 0x80 |
| 132 | |
| 133 | /* Subtypes of BRCM_HNBU: */ |
| 134 | |
| 135 | #define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */ |
| 136 | #define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */ |
| 137 | #define HNBU_BOARDREV 0x02 /* One byte board revision */ |
| 138 | #define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1) |
| 139 | * or 9 (sromrev > 1) bytes |
| 140 | */ |
| 141 | #define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */ |
| 142 | #define HNBU_CC 0x05 /* Default country code (sromrev == 1) */ |
| 143 | #define HNBU_AA 0x06 /* Antennas available */ |
| 144 | #define HNBU_AG 0x07 /* Antenna gain */ |
| 145 | #define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */ |
| 146 | #define HNBU_LEDS 0x09 /* LED set */ |
| 147 | #define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl) |
| 148 | * in rev 2 |
| 149 | */ |
| 150 | #define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */ |
| 151 | #define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */ |
| 152 | #define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */ |
| 153 | #define HNBU_PAPARMS5G 0x0e /* 5G PA params */ |
| 154 | #define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */ |
| 155 | #define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */ |
| 156 | #define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch, |
| 157 | * 2 bytes, rev 3. |
| 158 | */ |
| 159 | #define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch, |
| 160 | * 2 bytes, rev 3. |
| 161 | */ |
| 162 | #define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */ |
| 163 | #define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */ |
| 164 | #define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */ |
| 165 | #define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */ |
| 166 | #define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */ |
| 167 | #define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */ |
| 168 | #define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */ |
| 169 | #define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */ |
| 170 | #define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */ |
| 171 | #define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */ |
| 172 | #define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */ |
| 173 | #define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8 |
| 174 | * plus extra info appended. |
| 175 | */ |
| 176 | |
| 177 | /* sbtmstatelow */ |
| 178 | #define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */ |
| 179 | #define SBTML_INT_EN 0x20000 /* enable sb interrupt */ |
| 180 | |
| 181 | /* sbtmstatehigh */ |
| 182 | #define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */ |
| 183 | |
| 184 | #endif /* _SBPCMCIA_H */ |
| 185 | |
