| 1 | /* |
| 2 | * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions. |
| 3 | * |
| 4 | * Copyright 2007, Broadcom Corporation |
| 5 | * All Rights Reserved. |
| 6 | * |
| 7 | * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY |
| 8 | * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM |
| 9 | * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS |
| 10 | * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef _SBSDRAM_H |
| 15 | #define _SBSDRAM_H |
| 16 | |
| 17 | #ifndef _LANGUAGE_ASSEMBLY |
| 18 | |
| 19 | /* Sonics side: SDRAM core registers */ |
| 20 | typedef volatile struct sbsdramregs { |
| 21 | uint32 initcontrol; /* Generates external SDRAM initialization sequence */ |
| 22 | uint32 config; /* Initializes external SDRAM mode register */ |
| 23 | uint32 refresh; /* Controls external SDRAM refresh rate */ |
| 24 | uint32 pad1; |
| 25 | uint32 pad2; |
| 26 | } sbsdramregs_t; |
| 27 | |
| 28 | #endif /* !_LANGUAGE_ASSEMBLY */ |
| 29 | |
| 30 | /* SDRAM initialization control (initcontrol) register bits */ |
| 31 | #define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */ |
| 32 | #define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */ |
| 33 | #define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */ |
| 34 | #define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */ |
| 35 | #define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */ |
| 36 | #define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */ |
| 37 | #define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */ |
| 38 | #define SDRAM_RSVMb 0x0030 /* Use special SDRAM */ |
| 39 | #define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */ |
| 40 | #define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */ |
| 41 | #define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */ |
| 42 | #define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */ |
| 43 | #define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */ |
| 44 | |
| 45 | /* SDRAM configuration (config) register bits */ |
| 46 | #define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */ |
| 47 | #define SDRAM_BURST8 0x0001 /* Use burst of 8 */ |
| 48 | #define SDRAM_BURST4 0x0002 /* Use burst of 4 */ |
| 49 | #define SDRAM_BURST2 0x0003 /* Use burst of 2 */ |
| 50 | #define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */ |
| 51 | #define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */ |
| 52 | |
| 53 | /* SDRAM refresh control (refresh) register bits */ |
| 54 | #define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */ |
| 55 | #define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */ |
| 56 | |
| 57 | /* SDRAM Core default Init values (OCP ID 0x803) */ |
| 58 | #define SDRAM_INIT MEM4MX16X2 |
| 59 | #define SDRAM_CONFIG SDRAM_BURSTFULL |
| 60 | #define SDRAM_REFRESH SDRAM_REF(0x40) |
| 61 | |
| 62 | #define MEM1MX16 0x009 /* 2 MB */ |
| 63 | #define MEM1MX16X2 0x409 /* 4 MB */ |
| 64 | #define MEM2MX8X2 0x809 /* 4 MB */ |
| 65 | #define MEM2MX8X4 0xc09 /* 8 MB */ |
| 66 | #define MEM2MX32 0x439 /* 8 MB */ |
| 67 | #define MEM4MX16 0x019 /* 8 MB */ |
| 68 | #define MEM4MX16X2 0x419 /* 16 MB */ |
| 69 | #define MEM8MX8X2 0x819 /* 16 MB */ |
| 70 | #define MEM8MX16 0x829 /* 16 MB */ |
| 71 | #define MEM4MX32 0x429 /* 16 MB */ |
| 72 | #define MEM8MX8X4 0xc19 /* 32 MB */ |
| 73 | #define MEM8MX16X2 0xc29 /* 32 MB */ |
| 74 | |
| 75 | #endif /* _SBSDRAM_H */ |
| 76 | |
