| 1 | /* |
| 2 | * SPROM format definitions for the Broadcom 47xx and 43xx chip family. |
| 3 | * |
| 4 | * Copyright(c) 2002 Broadcom Corporation |
| 5 | */ |
| 6 | |
| 7 | #ifndef _SBSPROM_H |
| 8 | #define _SBSPROM_H |
| 9 | |
| 10 | #include "typedefs.h" |
| 11 | #include "bcmdevs.h" |
| 12 | |
| 13 | /* A word is this many bytes */ |
| 14 | #define SRW 2 |
| 15 | |
| 16 | /* offset into PCI config space for write enable bit */ |
| 17 | #define CFG_SROM_WRITABLE_OFFSET 0x88 |
| 18 | #define SROM_WRITEABLE 0x10 |
| 19 | |
| 20 | /* enumeration space consists of N contiguous 4Kbyte core register sets */ |
| 21 | #define SBCORES_BASE 0x18000000 |
| 22 | #define SBCORES_EACH 0x1000 |
| 23 | |
| 24 | /* offset from BAR0 for srom space */ |
| 25 | #define SROM_BASE 4096 |
| 26 | |
| 27 | /* number of 2-byte words in srom */ |
| 28 | #define SROM_SIZE 64 |
| 29 | |
| 30 | #define SROM_BYTES (SROM_SIZE * SRW) |
| 31 | |
| 32 | #define MAX_FN 4 |
| 33 | |
| 34 | /* Word 0, Hardware control */ |
| 35 | #define SROM_HWCTL 0 |
| 36 | #define HW_FUNMSK 0x000f |
| 37 | #define HW_FCLK 0x0200 |
| 38 | #define HW_CBM 0x0400 |
| 39 | #define HW_PIMSK 0xf000 |
| 40 | #define HW_PISHIFT 12 |
| 41 | #define HW_4301PISHIFT 13 |
| 42 | #define HW_PI4402 0x2 |
| 43 | #define HW_FUN4401 0x0001 |
| 44 | #define HW_FCLK4402 0x0000 |
| 45 | |
| 46 | /* Word 1, common-power/boot-rom */ |
| 47 | #define SROM_COMMPW 1 |
| 48 | /* boot rom present bit */ |
| 49 | #define BR_PRESSHIFT 8 |
| 50 | /* 15:9 for n; boot rom size is 2^(14 + n) bytes */ |
| 51 | #define BR_SIZESHIFT 9 |
| 52 | |
| 53 | /* Word 2, SubsystemId */ |
| 54 | #define SROM_SSID 2 |
| 55 | |
| 56 | /* Word 3, VendorId */ |
| 57 | #define SROM_VID 3 |
| 58 | |
| 59 | /* Function 0 info, function info length */ |
| 60 | #define SROM_FN0 4 |
| 61 | #define SROM_FNSZ 8 |
| 62 | |
| 63 | /* Within each function: */ |
| 64 | /* Word 0, deviceID */ |
| 65 | #define SRFN_DID 0 |
| 66 | |
| 67 | /* Words 1-2, ClassCode */ |
| 68 | #define SRFN_CCL 1 |
| 69 | /* Word 2, D0 Power */ |
| 70 | #define SRFN_CCHD0 2 |
| 71 | |
| 72 | /* Word 3, PME and D1D2D3 power */ |
| 73 | #define SRFN_PMED123 3 |
| 74 | |
| 75 | #define PME_IL 0 |
| 76 | #define PME_ENET0 1 |
| 77 | #define PME_ENET1 2 |
| 78 | #define PME_CODEC 3 |
| 79 | |
| 80 | #define PME_4402_ENET 0 |
| 81 | #define PME_4402_CODEC 1 |
| 82 | #define PME_4301_WL 2 |
| 83 | #define PMEREP_4402_ENET (PMERD3CV | PMERD3CA | PMERD3H | PMERD2 | PMERD1 | PMERD0 | PME) |
| 84 | |
| 85 | /* Word 4, Bar1 enable, pme reports */ |
| 86 | #define SRFN_B1PMER 4 |
| 87 | #define B1E 1 |
| 88 | #define B1SZMSK 0xe |
| 89 | #define B1SZSH 1 |
| 90 | #define PMERMSK 0x0ff0 |
| 91 | #define PME 0x0010 |
| 92 | #define PMERD0 0x0020 |
| 93 | #define PMERD1 0x0040 |
| 94 | #define PMERD2 0x0080 |
| 95 | #define PMERD3H 0x0100 |
| 96 | #define PMERD3CA 0x0200 |
| 97 | #define PMERD3CV 0x0400 |
| 98 | #define IGNCLKRR 0x0800 |
| 99 | #define B0LMSK 0xf000 |
| 100 | |
| 101 | /* Words 4-5, Bar0 Sonics value */ |
| 102 | #define SRFN_B0H 5 |
| 103 | /* Words 6-7, CIS Pointer */ |
| 104 | #define SRFN_CISL 6 |
| 105 | #define SRFN_CISH 7 |
| 106 | |
| 107 | /* Words 36-38: iLine MAC address */ |
| 108 | #define SROM_I_MACHI 36 |
| 109 | #define SROM_I_MACMID 37 |
| 110 | #define SROM_I_MACLO 38 |
| 111 | |
| 112 | /* Words 36-38: wireless0 MAC address on 43xx */ |
| 113 | #define SROM_W0_MACHI 36 |
| 114 | #define SROM_W0_MACMID 37 |
| 115 | #define SROM_W0_MACLO 38 |
| 116 | |
| 117 | /* Words 39-41: enet0 MAC address */ |
| 118 | #define SROM_E0_MACHI 39 |
| 119 | #define SROM_E0_MACMID 40 |
| 120 | #define SROM_E0_MACLO 41 |
| 121 | |
| 122 | /* Words 42-44: enet1 MAC address */ |
| 123 | #define SROM_E1_MACHI 42 |
| 124 | #define SROM_E1_MACMID 43 |
| 125 | #define SROM_E1_MACLO 44 |
| 126 | |
| 127 | /* Words 42-44: wireless1 MAC address on 4309 */ |
| 128 | #define SROM_W1_MACHI 42 |
| 129 | #define SROM_W1_MACMID 43 |
| 130 | #define SROM_W1_MACLO 44 |
| 131 | |
| 132 | #define SROM_EPHY 45 |
| 133 | |
| 134 | /* Word 46: BdRev & Antennas0/1 & ccLock for 430x */ |
| 135 | #define SROM_REV_AA_LOCK 46 |
| 136 | |
| 137 | /* Words 47-51 wl0 PA bx */ |
| 138 | #define SROM_WL0_PAB0 47 |
| 139 | #define SROM_WL0_PAB1 48 |
| 140 | #define SROM_WL0_PAB2 49 |
| 141 | #define SROM_WL0_PAB3 50 |
| 142 | #define SROM_WL0_PAB4 51 |
| 143 | |
| 144 | /* Word 52: wl0/wl1 MaxPower */ |
| 145 | #define SROM_WL_MAXPWR 52 |
| 146 | |
| 147 | /* Words 53-55 wl1 PA bx */ |
| 148 | #define SROM_WL1_PAB0 53 |
| 149 | #define SROM_WL1_PAB1 54 |
| 150 | #define SROM_WL1_PAB2 55 |
| 151 | |
| 152 | /* Woprd 56: itt */ |
| 153 | #define SROM_ITT 56 |
| 154 | |
| 155 | /* Words 59-62: OEM Space */ |
| 156 | #define SROM_WL_OEM 59 |
| 157 | #define SROM_OEM_SIZE 4 |
| 158 | |
| 159 | /* Contents for the srom */ |
| 160 | |
| 161 | #define BU4710_SSID 0x0400 |
| 162 | #define VSIM4710_SSID 0x0401 |
| 163 | #define QT4710_SSID 0x0402 |
| 164 | |
| 165 | #define BU4610_SSID 0x0403 |
| 166 | #define VSIM4610_SSID 0x0404 |
| 167 | |
| 168 | #define BU4307_SSID 0x0405 |
| 169 | #define BCM94301CB_SSID 0x0406 |
| 170 | #define BCM94301MP_SSID 0x0407 |
| 171 | #define BCM94307MP_SSID 0x0408 |
| 172 | #define AP4307_SSID 0x0409 |
| 173 | |
| 174 | #define BU4309_SSID 0x040a |
| 175 | #define BCM94309CB_SSID 0x040b |
| 176 | #define BCM94309MP_SSID 0x040c |
| 177 | #define AP4309_SSID 0x040d |
| 178 | |
| 179 | #define BU4402_SSID 0x4402 |
| 180 | |
| 181 | #define CLASS_OTHER 0x8000 |
| 182 | #define CLASS_ETHER 0x0000 |
| 183 | #define CLASS_NET 0x0002 |
| 184 | #define CLASS_COMM 0x0007 |
| 185 | #define CLASS_MODEM 0x0300 |
| 186 | #define CLASS_MIPS 0x3000 |
| 187 | #define CLASS_PROC 0x000b |
| 188 | #define CLASS_FLASH 0x0100 |
| 189 | #define CLASS_MEM 0x0005 |
| 190 | #define CLASS_SERIALBUS 0x000c |
| 191 | #define CLASS_OHCI 0x0310 |
| 192 | |
| 193 | /* Broadcom IEEE MAC addresses are 00:90:4c:xx:xx:xx */ |
| 194 | #define MACHI 0x90 |
| 195 | |
| 196 | #define MACMID_BU4710I 0x4c17 |
| 197 | #define MACMID_BU4710E0 0x4c18 |
| 198 | #define MACMID_BU4710E1 0x4c19 |
| 199 | |
| 200 | #define MACMID_94710R1I 0x4c1a |
| 201 | #define MACMID_94710R1E0 0x4c1b |
| 202 | #define MACMID_94710R1E1 0x4c1c |
| 203 | |
| 204 | #define MACMID_94710R4I 0x4c1d |
| 205 | #define MACMID_94710R4E0 0x4c1e |
| 206 | #define MACMID_94710R4E1 0x4c1f |
| 207 | |
| 208 | #define MACMID_94710DEVI 0x4c20 |
| 209 | #define MACMID_94710DEVE0 0x4c21 |
| 210 | #define MACMID_94710DEVE1 0x4c22 |
| 211 | |
| 212 | #define MACMID_BU4402 0x4c23 |
| 213 | |
| 214 | #define MACMID_BU4610I 0x4c24 |
| 215 | #define MACMID_BU4610E0 0x4c25 |
| 216 | #define MACMID_BU4610E1 0x4c26 |
| 217 | |
| 218 | #define MACMID_BU4307W 0x4c27 |
| 219 | #define MACMID_BU4307E 0x4c28 |
| 220 | |
| 221 | #define MACMID_94301CB 0x4c29 |
| 222 | |
| 223 | #define MACMID_94301MP 0x4c2a |
| 224 | |
| 225 | #define MACMID_94307MPW 0x4c2b |
| 226 | #define MACMID_94307MPE 0x4c2c |
| 227 | |
| 228 | #define MACMID_AP4307W 0x4c2d |
| 229 | #define MACMID_AP4307E 0x4c2e |
| 230 | |
| 231 | #define MACMID_BU4309W0 0x4c2f |
| 232 | #define MACMID_BU4309W1 0x4c30 |
| 233 | #define MACMID_BU4309E 0x4c31 |
| 234 | |
| 235 | #define MACMID_94309CBW0 0x4c32 |
| 236 | #define MACMID_94309CBW1 0x4c33 |
| 237 | |
| 238 | #define MACMID_94309MPW0 0x4c34 |
| 239 | #define MACMID_94309MPW1 0x4c35 |
| 240 | #define MACMID_94309MPE 0x4c36 |
| 241 | |
| 242 | #define MACMID_BU4401 0x4c37 |
| 243 | |
| 244 | /* Enet phy settings one or two singles or a dual */ |
| 245 | /* Bits 4-0 : MII address for enet0 (0x1f for not there */ |
| 246 | /* Bits 9-5 : MII address for enet1 (0x1f for not there */ |
| 247 | /* Bit 14 : Mdio for enet0 */ |
| 248 | /* Bit 15 : Mdio for enet1 */ |
| 249 | |
| 250 | /* bu4710 with only one phy on enet1 with address 7: */ |
| 251 | #define SROM_EPHY_ONE 0x80ff |
| 252 | |
| 253 | /* bu4710 with two individual phys, at 6 and 7, */ |
| 254 | /* each mdio connected to its own mac: */ |
| 255 | #define SROM_EPHY_TWO 0x80e6 |
| 256 | |
| 257 | /* bu4710 with a dual phy addresses 0 & 1, mdio-connected to enet0 */ |
| 258 | #define SROM_EPHY_DUAL 0x0001 |
| 259 | |
| 260 | /* r1 board with a dual phy at 0, 1 (NOT swapped and mdc0 */ |
| 261 | #define SROM_EPHY_R1 0x0010 |
| 262 | |
| 263 | /* r4 board with a single phy on enet0 at address 5 and a switch */ |
| 264 | /* chip on enet1 (speciall case: 0x1e */ |
| 265 | #define SROM_EPHY_R4 0x83e5 |
| 266 | |
| 267 | /* 4402 uses an internal phy at phyaddr 1; want mdcport == coreunit == 0 */ |
| 268 | #define SROM_EPHY_INTERNAL 0x0001 |
| 269 | |
| 270 | /* 4307 uses an external phy at phyaddr 0; want mdcport == coreunit == 0 */ |
| 271 | #define SROM_EPHY_ZERO 0x0000 |
| 272 | |
| 273 | #define SROM_VERS 0x0001 |
| 274 | |
| 275 | |
| 276 | #endif /* _SBSPROM_H */ |
| 277 | |
