Root/target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbutils.h

1/*
2 * Misc utility routines for accessing chip-specific features
3 * of Broadcom HNBU SiliconBackplane-based chips.
4 *
5 * Copyright 2007, Broadcom Corporation
6 * All Rights Reserved.
7 *
8 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12 *
13 */
14
15#ifndef _sbutils_h_
16#define _sbutils_h_
17
18/*
19 * Data structure to export all chip specific common variables
20 * public (read-only) portion of sbutils handle returned by
21 * sb_attach()/sb_kattach()
22*/
23
24struct sb_pub {
25
26    uint bustype; /* SB_BUS, PCI_BUS */
27    uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */
28    uint buscorerev; /* buscore rev */
29    uint buscoreidx; /* buscore index */
30    int ccrev; /* chip common core rev */
31    uint32 cccaps; /* chip common capabilities */
32    int pmurev; /* pmu core rev */
33    uint32 pmucaps; /* pmu capabilities */
34    uint boardtype; /* board type */
35    uint boardvendor; /* board vendor */
36    uint boardflags; /* board flags */
37    uint chip; /* chip number */
38    uint chiprev; /* chip revision */
39    uint chippkg; /* chip package option */
40    uint32 chipst; /* chip status */
41    uint sonicsrev; /* sonics backplane rev */
42    bool pr42780; /* whether PCIE 42780 WAR applies to this chip */
43    bool pr32414; /* whether 432414 WAR applis to the chip */
44};
45
46typedef const struct sb_pub sb_t;
47
48/*
49 * Many of the routines below take an 'sbh' handle as their first arg.
50 * Allocate this by calling sb_attach(). Free it by calling sb_detach().
51 * At any one time, the sbh is logically focused on one particular sb core
52 * (the "current core").
53 * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
54 */
55
56#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
57
58/* exported externs */
59extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
60                       void *sdh, char **vars, uint *varsz);
61extern sb_t *sb_kattach(osl_t *osh);
62extern void sb_detach(sb_t *sbh);
63extern uint sb_chip(sb_t *sbh);
64extern uint sb_chiprev(sb_t *sbh);
65extern uint sb_chipcrev(sb_t *sbh);
66extern uint sb_chippkg(sb_t *sbh);
67extern uint sb_pcirev(sb_t *sbh);
68extern bool sb_war16165(sb_t *sbh);
69extern uint sb_pcmciarev(sb_t *sbh);
70extern uint sb_boardvendor(sb_t *sbh);
71extern uint sb_boardtype(sb_t *sbh);
72extern uint sb_bus(sb_t *sbh);
73extern uint sb_buscoretype(sb_t *sbh);
74extern uint sb_buscorerev(sb_t *sbh);
75extern uint sb_corelist(sb_t *sbh, uint coreid[]);
76extern uint sb_coreid(sb_t *sbh);
77extern uint sb_flag(sb_t *sbh);
78extern uint sb_coreidx(sb_t *sbh);
79extern uint sb_coreunit(sb_t *sbh);
80extern uint sb_corevendor(sb_t *sbh);
81extern uint sb_corerev(sb_t *sbh);
82extern void *sb_osh(sb_t *sbh);
83extern void sb_setosh(sb_t *sbh, osl_t *osh);
84extern uint sb_corereg(sb_t *sbh, uint coreidx, uint regoff, uint mask, uint val);
85extern void *sb_coreregs(sb_t *sbh);
86extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
87extern void sb_coreflags_wo(sb_t *sbh, uint32 mask, uint32 val);
88extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
89extern bool sb_iscoreup(sb_t *sbh);
90extern uint sb_findcoreidx(sb_t *sbh, uint coreid, uint coreunit);
91extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
92extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
93extern int sb_corebist(sb_t *sbh);
94extern void sb_commit(sb_t *sbh);
95extern uint32 sb_base(uint32 admatch);
96extern uint32 sb_size(uint32 admatch);
97extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits);
98extern void sb_core_tofixup(sb_t *sbh);
99extern void sb_core_disable(sb_t *sbh, uint32 bits);
100extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
101extern uint32 sb_clock(sb_t *sbh);
102extern uint32 sb_alp_clock(sb_t *sbh);
103extern void sb_pci_setup(sb_t *sbh, uint coremask);
104extern void sb_pcmcia_init(sb_t *sbh);
105extern void sb_watchdog(sb_t *sbh, uint ticks);
106extern void *sb_gpiosetcore(sb_t *sbh);
107extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
108extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
109extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
110extern uint32 sb_gpioin(sb_t *sbh);
111extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
112extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
113extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
114extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
115extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
116extern uint32 sb_gpiopull(sb_t *sbh, bool updown, uint32 mask, uint32 val);
117extern uint32 sb_gpioevent(sb_t *sbh, uint regtype, uint32 mask, uint32 val);
118extern uint32 sb_gpio_int_enable(sb_t *sbh, bool enable);
119
120/* GPIO event handlers */
121typedef void (*gpio_handler_t)(uint32 stat, void *arg);
122
123extern void *sb_gpio_handler_register(sb_t *sbh, uint32 event,
124    bool level, gpio_handler_t cb, void *arg);
125extern void sb_gpio_handler_unregister(sb_t *sbh, void* gpioh);
126extern void sb_gpio_handler_process(sb_t *sbh);
127
128extern void sb_clkctl_init(sb_t *sbh);
129extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
130extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
131extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
132extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
133                                      void *intrsenabled_fn, void *intr_arg);
134extern void sb_deregister_intr_callback(sb_t *sbh);
135extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to, uint idx);
136extern uint16 sb_d11_devid(sb_t *sbh);
137extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
138                        uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
139                        uint8 *pciheader);
140extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
141extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
142extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
143extern bool sb_backplane64(sb_t *sbh);
144extern void sb_btcgpiowar(sb_t *sbh);
145
146
147#if defined(BCMDBG_ASSERT)
148extern bool sb_taclear(sb_t *sbh);
149#endif
150
151#ifdef BCMDBG
152extern void sb_dump(sb_t *sbh, struct bcmstrbuf *b);
153extern void sb_dumpregs(sb_t *sbh, struct bcmstrbuf *b);
154extern void sb_view(sb_t *sbh);
155extern void sb_viewall(sb_t *sbh);
156extern void sb_clkctl_dump(sb_t *sbh, struct bcmstrbuf *b);
157extern uint8 sb_pcieL1plldown(sb_t *sbh);
158extern uint32 sb_pcielcreg(sb_t *sbh, uint32 mask, uint32 val);
159#endif
160
161extern bool sb_deviceremoved(sb_t *sbh);
162extern uint32 sb_socram_size(sb_t *sbh);
163
164/*
165* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
166* The returned path is NULL terminated and has trailing '/'.
167* Return 0 on success, nonzero otherwise.
168*/
169extern int sb_devpath(sb_t *sbh, char *path, int size);
170/* Read variable with prepending the devpath to the name */
171extern char *sb_getdevpathvar(sb_t *sbh, const char *name);
172extern int sb_getdevpathintvar(sb_t *sbh, const char *name);
173
174extern uint8 sb_pcieclkreq(sb_t *sbh, uint32 mask, uint32 val);
175extern void sb_war42780_clkreq(sb_t *sbh, bool clkreq);
176extern void sb_pci_sleep(sb_t *sbh);
177extern void sb_pci_down(sb_t *sbh);
178extern void sb_pci_up(sb_t *sbh);
179
180/* Wake-on-wireless-LAN (WOWL) */
181extern bool sb_pci_pmecap(sb_t *sbh);
182extern bool sb_pci_pmeclr(sb_t *sbh);
183extern void sb_pci_pmeen(sb_t *sbh);
184
185/* clkctl xtal what flags */
186#define XTAL 0x1 /* primary crystal oscillator (2050) */
187#define PLL 0x2 /* main chip pll */
188
189/* clkctl clk mode */
190#define CLK_FAST 0 /* force fast (pll) clock */
191#define CLK_DYNAMIC 2 /* enable dynamic clock control */
192
193
194/* GPIO usage priorities */
195#define GPIO_DRV_PRIORITY 0 /* Driver */
196#define GPIO_APP_PRIORITY 1 /* Application */
197#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
198
199/* GPIO pull up/down */
200#define GPIO_PULLUP 0
201#define GPIO_PULLDN 1
202
203/* GPIO event regtype */
204#define GPIO_REGEVT 0 /* GPIO register event */
205#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
206#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
207
208/* device path */
209#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
210
211#endif /* _sbutils_h_ */
212

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