Root/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c

1/*
2 * Low-Level PCI and SB support for BCM47xx (Linux support code)
3 *
4 * Copyright 2006, Broadcom Corporation
5 * All Rights Reserved.
6 *
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11 *
12 */
13
14#include <linux/config.h>
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/sched.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <asm/io.h>
22#include <asm/irq.h>
23#include <asm/paccess.h>
24
25#include <typedefs.h>
26#include <osl.h>
27#include <sbconfig.h>
28#include <sbutils.h>
29#include <hndpci.h>
30#include <pcicfg.h>
31#include <bcmdevs.h>
32#include <bcmnvram.h>
33
34/* Global SB handle */
35extern sb_t *bcm947xx_sbh;
36extern spinlock_t bcm947xx_sbh_lock;
37
38/* Convenience */
39#define sbh bcm947xx_sbh
40#define sbh_lock bcm947xx_sbh_lock
41
42static int
43sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
44{
45    unsigned long flags;
46    int ret;
47
48    spin_lock_irqsave(&sbh_lock, flags);
49    ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
50        PCI_FUNC(dev->devfn), where, value, sizeof(*value));
51    spin_unlock_irqrestore(&sbh_lock, flags);
52    return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
53}
54
55static int
56sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
57{
58    unsigned long flags;
59    int ret;
60
61    spin_lock_irqsave(&sbh_lock, flags);
62    ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
63        PCI_FUNC(dev->devfn), where, value, sizeof(*value));
64    spin_unlock_irqrestore(&sbh_lock, flags);
65    return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
66}
67
68static int
69sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
70{
71    unsigned long flags;
72    int ret;
73
74    spin_lock_irqsave(&sbh_lock, flags);
75    ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
76        PCI_FUNC(dev->devfn), where, value, sizeof(*value));
77    spin_unlock_irqrestore(&sbh_lock, flags);
78    return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
79}
80
81static int
82sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
83{
84    unsigned long flags;
85    int ret;
86
87    spin_lock_irqsave(&sbh_lock, flags);
88    ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
89        PCI_FUNC(dev->devfn), where, &value, sizeof(value));
90    spin_unlock_irqrestore(&sbh_lock, flags);
91    return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
92}
93
94static int
95sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
96{
97    unsigned long flags;
98    int ret;
99
100    spin_lock_irqsave(&sbh_lock, flags);
101    ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
102        PCI_FUNC(dev->devfn), where, &value, sizeof(value));
103    spin_unlock_irqrestore(&sbh_lock, flags);
104    return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
105}
106
107static int
108sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
109{
110    unsigned long flags;
111    int ret;
112
113    spin_lock_irqsave(&sbh_lock, flags);
114    ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
115        PCI_FUNC(dev->devfn), where, &value, sizeof(value));
116    spin_unlock_irqrestore(&sbh_lock, flags);
117    return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
118}
119
120static struct pci_ops pcibios_ops = {
121    sbpci_read_config_byte,
122    sbpci_read_config_word,
123    sbpci_read_config_dword,
124    sbpci_write_config_byte,
125    sbpci_write_config_word,
126    sbpci_write_config_dword
127};
128
129
130void __init
131pcibios_init(void)
132{
133    ulong flags;
134
135    if (!(sbh = sb_kattach(SB_OSH)))
136        panic("sb_kattach failed");
137    spin_lock_init(&sbh_lock);
138
139    spin_lock_irqsave(&sbh_lock, flags);
140    sbpci_init(sbh);
141    spin_unlock_irqrestore(&sbh_lock, flags);
142
143    set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
144    mdelay(300); /* workaround for atheros cards */
145
146    /* Scan the SB bus */
147    pci_scan_bus(0, &pcibios_ops, NULL);
148
149}
150
151char * __init
152pcibios_setup(char *str)
153{
154    if (!strncmp(str, "ban=", 4)) {
155        sbpci_ban(simple_strtoul(str + 4, NULL, 0));
156        return NULL;
157    }
158
159    return (str);
160}
161
162static u32 pci_iobase = 0x100;
163static u32 pci_membase = SB_PCI_DMA;
164static u32 pcmcia_membase = 0x40004000;
165
166void __init
167pcibios_fixup_bus(struct pci_bus *b)
168{
169    struct list_head *ln;
170    struct pci_dev *d;
171    struct resource *res;
172    int pos, size;
173    u32 *base;
174    u8 irq;
175
176    printk("PCI: Fixing up bus %d\n", b->number);
177
178    /* Fix up SB */
179    if (b->number == 0) {
180        for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
181            d = pci_dev_b(ln);
182            /* Fix up interrupt lines */
183            pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
184            d->irq = irq + 2;
185            pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
186        }
187    }
188
189    /* Fix up external PCI */
190    else {
191        for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
192            d = pci_dev_b(ln);
193            /* Fix up resource bases */
194            for (pos = 0; pos < 6; pos++) {
195                res = &d->resource[pos];
196                base = (res->flags & IORESOURCE_IO) ? &pci_iobase : ((b->number == 2) ? &pcmcia_membase : &pci_membase);
197                if (res->end) {
198                    size = res->end - res->start + 1;
199                    if (*base & (size - 1))
200                        *base = (*base + size) & ~(size - 1);
201                    res->start = *base;
202                    res->end = res->start + size - 1;
203                    *base += size;
204                    pci_write_config_dword(d,
205                        PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
206                }
207                /* Fix up PCI bridge BAR0 only */
208                if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
209                    break;
210            }
211            /* Fix up interrupt lines */
212            if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
213                d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
214            pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
215        }
216    }
217}
218
219unsigned int
220pcibios_assign_all_busses(void)
221{
222    return 1;
223}
224
225void
226pcibios_align_resource(void *data, struct resource *res,
227    unsigned long size, unsigned long align)
228{
229}
230
231int
232pcibios_enable_resources(struct pci_dev *dev)
233{
234    u16 cmd, old_cmd;
235    int idx;
236    struct resource *r;
237
238    /* External PCI only */
239    if (dev->bus->number == 0)
240        return 0;
241
242    pci_read_config_word(dev, PCI_COMMAND, &cmd);
243    old_cmd = cmd;
244    for (idx = 0; idx < 6; idx++) {
245        r = &dev->resource[idx];
246        if (r->flags & IORESOURCE_IO)
247            cmd |= PCI_COMMAND_IO;
248        if (r->flags & IORESOURCE_MEM)
249            cmd |= PCI_COMMAND_MEMORY;
250    }
251    if (dev->resource[PCI_ROM_RESOURCE].start)
252        cmd |= PCI_COMMAND_MEMORY;
253    if (cmd != old_cmd) {
254        printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
255        pci_write_config_word(dev, PCI_COMMAND, cmd);
256    }
257    return 0;
258}
259
260int
261pcibios_enable_device(struct pci_dev *dev, int mask)
262{
263    ulong flags;
264    uint coreidx;
265    void *regs;
266
267    /* External PCI device enable */
268    if (dev->bus->number != 0)
269        return pcibios_enable_resources(dev);
270
271    /* These cores come out of reset enabled */
272    if (dev->device == SB_MIPS ||
273        dev->device == SB_MIPS33 ||
274        dev->device == SB_EXTIF ||
275        dev->device == SB_CC)
276        return 0;
277
278    spin_lock_irqsave(&sbh_lock, flags);
279    coreidx = sb_coreidx(sbh);
280    regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
281    if (!regs)
282        return PCIBIOS_DEVICE_NOT_FOUND;
283
284    /*
285     * The USB core requires a special bit to be set during core
286     * reset to enable host (OHCI) mode. Resetting the SB core in
287     * pcibios_enable_device() is a hack for compatibility with
288     * vanilla usb-ohci so that it does not have to know about
289     * SB. A driver that wants to use the USB core in device mode
290     * should know about SB and should reset the bit back to 0
291     * after calling pcibios_enable_device().
292     */
293    if (sb_coreid(sbh) == SB_USB) {
294        printk(KERN_INFO "SB USB 1.1 init\n");
295        sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
296        sb_core_reset(sbh, 1 << 29, 0);
297    }
298    /*
299     * USB 2.0 special considerations:
300     *
301     * 1. Since the core supports both OHCI and EHCI functions, it must
302     * only be reset once.
303     *
304     * 2. In addition to the standard SB reset sequence, the Host Control
305     * Register must be programmed to bring the USB core and various
306     * phy components out of reset.
307     */
308    else if (sb_coreid(sbh) == SB_USB20H) {
309        
310        uint corerev = sb_corerev(sbh);
311
312        printk(KERN_INFO "SB USB20H init\n");
313        printk(KERN_INFO "SB COREREV: %d\n", corerev);
314        
315        if (!sb_iscoreup(sbh)) {
316                        
317            printk(KERN_INFO "SB USB20H resetting\n");
318
319            sb_core_reset(sbh, 0, 0);
320            writel(0x7FF, (ulong)regs + 0x200);
321            udelay(1);
322        }
323        /* PRxxxx: War for 5354 failures. */
324        if (corerev == 1 || corerev == 2) {
325            uint32 tmp;
326
327            /* Change Flush control reg */
328            tmp = readl((uintptr)regs + 0x400);
329            tmp &= ~8;
330            writel(tmp, (uintptr)regs + 0x400);
331            tmp = readl((uintptr)regs + 0x400);
332            printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp);
333
334            /* Change Shim control reg */
335            tmp = readl((uintptr)regs + 0x304);
336            tmp &= ~0x100;
337            writel(tmp, (uintptr)regs + 0x304);
338            tmp = readl((uintptr)regs + 0x304);
339            printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp);
340        }
341
342    } else
343        sb_core_reset(sbh, 0, 0);
344
345    sb_setcoreidx(sbh, coreidx);
346    spin_unlock_irqrestore(&sbh_lock, flags);
347
348    return 0;
349}
350
351void
352pcibios_update_resource(struct pci_dev *dev, struct resource *root,
353    struct resource *res, int resource)
354{
355    unsigned long where, size;
356    u32 reg;
357
358    /* External PCI only */
359    if (dev->bus->number == 0)
360        return;
361
362    where = PCI_BASE_ADDRESS_0 + (resource * 4);
363    size = res->end - res->start;
364    pci_read_config_dword(dev, where, &reg);
365    
366    if (dev->bus->number == 1)
367        reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
368    else
369        reg = res->start;
370
371    pci_write_config_dword(dev, where, reg);
372}
373
374static void __init
375quirk_sbpci_bridge(struct pci_dev *dev)
376{
377    if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
378        return;
379
380    printk("PCI: Fixing up bridge\n");
381
382    /* Enable PCI bridge bus mastering and memory space */
383    pci_set_master(dev);
384    pcibios_enable_resources(dev);
385
386    /* Enable PCI bridge BAR1 prefetch and burst */
387    pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
388}
389
390struct pci_fixup pcibios_fixups[] = {
391    { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
392    { 0 }
393};
394
395/*
396 * If we set up a device for bus mastering, we need to check the latency
397 * timer as certain crappy BIOSes forget to set it properly.
398 */
399unsigned int pcibios_max_latency = 255;
400
401void pcibios_set_master(struct pci_dev *dev)
402{
403    u8 lat;
404    pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
405    if (lat < 16)
406        lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
407    else if (lat > pcibios_max_latency)
408        lat = pcibios_max_latency;
409    else
410        return;
411    printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
412    pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
413}
414
415

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