| 1 | /* |
| 2 | * ADM6996 switch driver |
| 3 | * |
| 4 | * Copyright (c) 2008 Felix Fietkau <nbd@openwrt.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License v2 as published by the |
| 8 | * Free Software Foundation |
| 9 | */ |
| 10 | #ifndef __ADM6996_H |
| 11 | #define __ADM6996_H |
| 12 | |
| 13 | #define ADM_PHY_PORTS 5 |
| 14 | #define ADM_CPU_PORT 5 |
| 15 | #define ADM_WAN_PORT 0 /* FIXME: dynamic ? */ |
| 16 | |
| 17 | enum admreg { |
| 18 | ADM_EEPROM_BASE = 0x0, |
| 19 | ADM_P0_CFG = ADM_EEPROM_BASE + 1, |
| 20 | ADM_P1_CFG = ADM_EEPROM_BASE + 3, |
| 21 | ADM_P2_CFG = ADM_EEPROM_BASE + 5, |
| 22 | ADM_P3_CFG = ADM_EEPROM_BASE + 7, |
| 23 | ADM_P4_CFG = ADM_EEPROM_BASE + 8, |
| 24 | ADM_P5_CFG = ADM_EEPROM_BASE + 9, |
| 25 | ADM_EEPROM_EXT_BASE = 0x40, |
| 26 | ADM_COUNTER_BASE = 0xa0, |
| 27 | ADM_SIG0 = ADM_COUNTER_BASE + 0, |
| 28 | ADM_SIG1 = ADM_COUNTER_BASE + 1, |
| 29 | ADM_PHY_BASE = 0x200, |
| 30 | #define ADM_PHY_PORT(n) (ADM_PHY_BASE + (0x20 * n)) |
| 31 | }; |
| 32 | |
| 33 | /* Chip identification patterns */ |
| 34 | #define ADM_SIG0_MASK 0xfff0 |
| 35 | #define ADM_SIG0_VAL 0x1020 |
| 36 | #define ADM_SIG1_MASK 0xffff |
| 37 | #define ADM_SIG1_VAL 0x0007 |
| 38 | |
| 39 | enum { |
| 40 | ADM_PHYCFG_COLTST = (1 << 7), /* Enable collision test */ |
| 41 | ADM_PHYCFG_DPLX = (1 << 8), /* Enable full duplex */ |
| 42 | ADM_PHYCFG_ANEN_RST = (1 << 9), /* Restart auto negotiation (self clear) */ |
| 43 | ADM_PHYCFG_ISO = (1 << 10), /* Isolate PHY */ |
| 44 | ADM_PHYCFG_PDN = (1 << 11), /* Power down PHY */ |
| 45 | ADM_PHYCFG_ANEN = (1 << 12), /* Enable auto negotiation */ |
| 46 | ADM_PHYCFG_SPEED_100 = (1 << 13), /* Enable 100 Mbit/s */ |
| 47 | ADM_PHYCFG_LPBK = (1 << 14), /* Enable loopback operation */ |
| 48 | ADM_PHYCFG_RST = (1 << 15), /* Reset the port (self clear) */ |
| 49 | ADM_PHYCFG_INIT = ( |
| 50 | ADM_PHYCFG_RST | |
| 51 | ADM_PHYCFG_SPEED_100 | |
| 52 | ADM_PHYCFG_ANEN | |
| 53 | ADM_PHYCFG_ANEN_RST |
| 54 | ) |
| 55 | }; |
| 56 | |
| 57 | enum { |
| 58 | ADM_PORTCFG_FC = (1 << 0), /* Enable 802.x flow control */ |
| 59 | ADM_PORTCFG_AN = (1 << 1), /* Enable auto-negotiation */ |
| 60 | ADM_PORTCFG_SPEED_100 = (1 << 2), /* Enable 100 Mbit/s */ |
| 61 | ADM_PORTCFG_DPLX = (1 << 3), /* Enable full duplex */ |
| 62 | ADM_PORTCFG_OT = (1 << 4), /* Output tagged packets */ |
| 63 | ADM_PORTCFG_PD = (1 << 5), /* Port disable */ |
| 64 | ADM_PORTCFG_TV_PRIO = (1 << 6), /* 0 = VLAN based priority |
| 65 | * 1 = TOS based priority */ |
| 66 | ADM_PORTCFG_PPE = (1 << 7), /* Port based priority enable */ |
| 67 | ADM_PORTCFG_PP_S = (1 << 8), /* Port based priority, 2 bits */ |
| 68 | ADM_PORTCFG_PVID_BASE = (1 << 10), /* Primary VLAN id, 4 bits */ |
| 69 | ADM_PORTCFG_FSE = (1 << 14), /* Fx select enable */ |
| 70 | ADM_PORTCFG_CAM = (1 << 15), /* Crossover Auto MDIX */ |
| 71 | |
| 72 | ADM_PORTCFG_INIT = ( |
| 73 | ADM_PORTCFG_FC | |
| 74 | ADM_PORTCFG_AN | |
| 75 | ADM_PORTCFG_SPEED_100 | |
| 76 | ADM_PORTCFG_DPLX | |
| 77 | ADM_PORTCFG_CAM |
| 78 | ), |
| 79 | ADM_PORTCFG_CPU = ( |
| 80 | ADM_PORTCFG_FC | |
| 81 | ADM_PORTCFG_SPEED_100 | |
| 82 | ADM_PORTCFG_OT | |
| 83 | ADM_PORTCFG_DPLX |
| 84 | ), |
| 85 | }; |
| 86 | |
| 87 | #define ADM_PORTCFG_PPID(N) ((n & 0x3) << 8) |
| 88 | #define ADM_PORTCFG_PVID(n) ((n & 0xf) << 10) |
| 89 | |
| 90 | static const u8 adm_portcfg[] = { |
| 91 | [0] = ADM_P0_CFG, |
| 92 | [1] = ADM_P1_CFG, |
| 93 | [2] = ADM_P2_CFG, |
| 94 | [3] = ADM_P3_CFG, |
| 95 | [4] = ADM_P4_CFG, |
| 96 | [5] = ADM_P5_CFG, |
| 97 | }; |
| 98 | |
| 99 | /* |
| 100 | * Split the register address in phy id and register |
| 101 | * it will get combined again by the mdio bus op |
| 102 | */ |
| 103 | #define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f) |
| 104 | |
| 105 | #endif |
| 106 | |
