| 1 | --- a/drivers/ssb/driver_chipcommon.c |
| 2 | +++ b/drivers/ssb/driver_chipcommon.c |
| 3 | @@ -373,6 +373,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c |
| 4 | { |
| 5 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); |
| 6 | } |
| 7 | +EXPORT_SYMBOL(ssb_chipco_gpio_control); |
| 8 | |
| 9 | u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) |
| 10 | { |
| 11 | --- a/drivers/ssb/driver_chipcommon_pmu.c |
| 12 | +++ b/drivers/ssb/driver_chipcommon_pmu.c |
| 13 | @@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_ |
| 14 | case 0x5354: |
| 15 | ssb_pmu0_pllinit_r0(cc, crystalfreq); |
| 16 | break; |
| 17 | + case 0x4322: |
| 18 | + if (cc->pmu.rev == 2) { |
| 19 | + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A); |
| 20 | + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0); |
| 21 | + } |
| 22 | + break; |
| 23 | default: |
| 24 | ssb_printk(KERN_ERR PFX |
| 25 | "ERROR: PLL init unknown for device %04X\n", |
| 26 | @@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc |
| 27 | |
| 28 | switch (bus->chip_id) { |
| 29 | case 0x4312: |
| 30 | + case 0x4322: |
| 31 | /* We keep the default settings: |
| 32 | * min_msk = 0xCBB |
| 33 | * max_msk = 0x7FFFF |
| 34 | --- a/drivers/ssb/driver_gige.c |
| 35 | +++ b/drivers/ssb/driver_gige.c |
| 36 | @@ -12,6 +12,7 @@ |
| 37 | #include <linux/ssb/ssb_driver_gige.h> |
| 38 | #include <linux/pci.h> |
| 39 | #include <linux/pci_regs.h> |
| 40 | +#include <linux/slab.h> |
| 41 | |
| 42 | |
| 43 | /* |
| 44 | --- a/drivers/ssb/driver_mipscore.c |
| 45 | +++ b/drivers/ssb/driver_mipscore.c |
| 46 | @@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco |
| 47 | set_irq(dev, irq++); |
| 48 | } |
| 49 | break; |
| 50 | - /* fallthrough */ |
| 51 | case SSB_DEV_PCI: |
| 52 | case SSB_DEV_ETHERNET: |
| 53 | case SSB_DEV_ETHERNET_GBIT: |
| 54 | @@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco |
| 55 | set_irq(dev, irq++); |
| 56 | break; |
| 57 | } |
| 58 | + /* fallthrough */ |
| 59 | + case SSB_DEV_EXTIF: |
| 60 | + set_irq(dev, 0); |
| 61 | + break; |
| 62 | } |
| 63 | } |
| 64 | ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n"); |
| 65 | --- a/drivers/ssb/driver_pcicore.c |
| 66 | +++ b/drivers/ssb/driver_pcicore.c |
| 67 | @@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore |
| 68 | .pci_ops = &ssb_pcicore_pciops, |
| 69 | .io_resource = &ssb_pcicore_io_resource, |
| 70 | .mem_resource = &ssb_pcicore_mem_resource, |
| 71 | - .mem_offset = 0x24000000, |
| 72 | }; |
| 73 | |
| 74 | -static u32 ssb_pcicore_pcibus_iobase = 0x100; |
| 75 | -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA; |
| 76 | - |
| 77 | /* This function is called when doing a pci_enable_device(). |
| 78 | * We must first check if the device is a device on the PCI-core bridge. */ |
| 79 | int ssb_pcicore_plat_dev_init(struct pci_dev *d) |
| 80 | { |
| 81 | - struct resource *res; |
| 82 | - int pos, size; |
| 83 | - u32 *base; |
| 84 | - |
| 85 | if (d->bus->ops != &ssb_pcicore_pciops) { |
| 86 | /* This is not a device on the PCI-core bridge. */ |
| 87 | return -ENODEV; |
| 88 | @@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci |
| 89 | ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", |
| 90 | pci_name(d)); |
| 91 | |
| 92 | - /* Fix up resource bases */ |
| 93 | - for (pos = 0; pos < 6; pos++) { |
| 94 | - res = &d->resource[pos]; |
| 95 | - if (res->flags & IORESOURCE_IO) |
| 96 | - base = &ssb_pcicore_pcibus_iobase; |
| 97 | - else |
| 98 | - base = &ssb_pcicore_pcibus_membase; |
| 99 | - res->flags |= IORESOURCE_PCI_FIXED; |
| 100 | - if (res->end) { |
| 101 | - size = res->end - res->start + 1; |
| 102 | - if (*base & (size - 1)) |
| 103 | - *base = (*base + size) & ~(size - 1); |
| 104 | - res->start = *base; |
| 105 | - res->end = res->start + size - 1; |
| 106 | - *base += size; |
| 107 | - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start); |
| 108 | - } |
| 109 | - /* Fix up PCI bridge BAR0 only */ |
| 110 | - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0) |
| 111 | - break; |
| 112 | - } |
| 113 | /* Fix up interrupt lines */ |
| 114 | d->irq = ssb_mips_irq(extpci_core->dev) + 2; |
| 115 | pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); |
| 116 | @@ -551,13 +522,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc |
| 117 | might_sleep_if(pdev->id.coreid != SSB_DEV_PCI); |
| 118 | |
| 119 | /* Enable interrupts for this device. */ |
| 120 | - if (bus->host_pci && |
| 121 | - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) { |
| 122 | + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) { |
| 123 | u32 coremask; |
| 124 | |
| 125 | /* Calculate the "coremask" for the device. */ |
| 126 | coremask = (1 << dev->core_index); |
| 127 | |
| 128 | + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI); |
| 129 | err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); |
| 130 | if (err) |
| 131 | goto out; |
| 132 | --- a/drivers/ssb/main.c |
| 133 | +++ b/drivers/ssb/main.c |
| 134 | @@ -18,6 +18,7 @@ |
| 135 | #include <linux/dma-mapping.h> |
| 136 | #include <linux/pci.h> |
| 137 | #include <linux/mmc/sdio_func.h> |
| 138 | +#include <linux/slab.h> |
| 139 | |
| 140 | #include <pcmcia/cs_types.h> |
| 141 | #include <pcmcia/cs.h> |
| 142 | @@ -140,6 +141,19 @@ static void ssb_device_put(struct ssb_de |
| 143 | put_device(dev->dev); |
| 144 | } |
| 145 | |
| 146 | +static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv) |
| 147 | +{ |
| 148 | + if (drv) |
| 149 | + get_driver(&drv->drv); |
| 150 | + return drv; |
| 151 | +} |
| 152 | + |
| 153 | +static inline void ssb_driver_put(struct ssb_driver *drv) |
| 154 | +{ |
| 155 | + if (drv) |
| 156 | + put_driver(&drv->drv); |
| 157 | +} |
| 158 | + |
| 159 | static int ssb_device_resume(struct device *dev) |
| 160 | { |
| 161 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); |
| 162 | @@ -210,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus) |
| 163 | EXPORT_SYMBOL(ssb_bus_suspend); |
| 164 | |
| 165 | #ifdef CONFIG_SSB_SPROM |
| 166 | -int ssb_devices_freeze(struct ssb_bus *bus) |
| 167 | +/** ssb_devices_freeze - Freeze all devices on the bus. |
| 168 | + * |
| 169 | + * After freezing no device driver will be handling a device |
| 170 | + * on this bus anymore. ssb_devices_thaw() must be called after |
| 171 | + * a successful freeze to reactivate the devices. |
| 172 | + * |
| 173 | + * @bus: The bus. |
| 174 | + * @ctx: Context structure. Pass this to ssb_devices_thaw(). |
| 175 | + */ |
| 176 | +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx) |
| 177 | { |
| 178 | - struct ssb_device *dev; |
| 179 | - struct ssb_driver *drv; |
| 180 | - int err = 0; |
| 181 | - int i; |
| 182 | - pm_message_t state = PMSG_FREEZE; |
| 183 | + struct ssb_device *sdev; |
| 184 | + struct ssb_driver *sdrv; |
| 185 | + unsigned int i; |
| 186 | + |
| 187 | + memset(ctx, 0, sizeof(*ctx)); |
| 188 | + ctx->bus = bus; |
| 189 | + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen)); |
| 190 | |
| 191 | - /* First check that we are capable to freeze all devices. */ |
| 192 | for (i = 0; i < bus->nr_devices; i++) { |
| 193 | - dev = &(bus->devices[i]); |
| 194 | - if (!dev->dev || |
| 195 | - !dev->dev->driver || |
| 196 | - !device_is_registered(dev->dev)) |
| 197 | - continue; |
| 198 | - drv = drv_to_ssb_drv(dev->dev->driver); |
| 199 | - if (!drv) |
| 200 | + sdev = ssb_device_get(&bus->devices[i]); |
| 201 | + |
| 202 | + if (!sdev->dev || !sdev->dev->driver || |
| 203 | + !device_is_registered(sdev->dev)) { |
| 204 | + ssb_device_put(sdev); |
| 205 | continue; |
| 206 | - if (!drv->suspend) { |
| 207 | - /* Nope, can't suspend this one. */ |
| 208 | - return -EOPNOTSUPP; |
| 209 | } |
| 210 | - } |
| 211 | - /* Now suspend all devices */ |
| 212 | - for (i = 0; i < bus->nr_devices; i++) { |
| 213 | - dev = &(bus->devices[i]); |
| 214 | - if (!dev->dev || |
| 215 | - !dev->dev->driver || |
| 216 | - !device_is_registered(dev->dev)) |
| 217 | + sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver)); |
| 218 | + if (!sdrv || SSB_WARN_ON(!sdrv->remove)) { |
| 219 | + ssb_device_put(sdev); |
| 220 | continue; |
| 221 | - drv = drv_to_ssb_drv(dev->dev->driver); |
| 222 | - if (!drv) |
| 223 | - continue; |
| 224 | - err = drv->suspend(dev, state); |
| 225 | - if (err) { |
| 226 | - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n", |
| 227 | - dev_name(dev->dev)); |
| 228 | - goto err_unwind; |
| 229 | } |
| 230 | + sdrv->remove(sdev); |
| 231 | + ctx->device_frozen[i] = 1; |
| 232 | } |
| 233 | |
| 234 | return 0; |
| 235 | -err_unwind: |
| 236 | - for (i--; i >= 0; i--) { |
| 237 | - dev = &(bus->devices[i]); |
| 238 | - if (!dev->dev || |
| 239 | - !dev->dev->driver || |
| 240 | - !device_is_registered(dev->dev)) |
| 241 | - continue; |
| 242 | - drv = drv_to_ssb_drv(dev->dev->driver); |
| 243 | - if (!drv) |
| 244 | - continue; |
| 245 | - if (drv->resume) |
| 246 | - drv->resume(dev); |
| 247 | - } |
| 248 | - return err; |
| 249 | } |
| 250 | |
| 251 | -int ssb_devices_thaw(struct ssb_bus *bus) |
| 252 | +/** ssb_devices_thaw - Unfreeze all devices on the bus. |
| 253 | + * |
| 254 | + * This will re-attach the device drivers and re-init the devices. |
| 255 | + * |
| 256 | + * @ctx: The context structure from ssb_devices_freeze() |
| 257 | + */ |
| 258 | +int ssb_devices_thaw(struct ssb_freeze_context *ctx) |
| 259 | { |
| 260 | - struct ssb_device *dev; |
| 261 | - struct ssb_driver *drv; |
| 262 | - int err; |
| 263 | - int i; |
| 264 | + struct ssb_bus *bus = ctx->bus; |
| 265 | + struct ssb_device *sdev; |
| 266 | + struct ssb_driver *sdrv; |
| 267 | + unsigned int i; |
| 268 | + int err, result = 0; |
| 269 | |
| 270 | for (i = 0; i < bus->nr_devices; i++) { |
| 271 | - dev = &(bus->devices[i]); |
| 272 | - if (!dev->dev || |
| 273 | - !dev->dev->driver || |
| 274 | - !device_is_registered(dev->dev)) |
| 275 | + if (!ctx->device_frozen[i]) |
| 276 | continue; |
| 277 | - drv = drv_to_ssb_drv(dev->dev->driver); |
| 278 | - if (!drv) |
| 279 | + sdev = &bus->devices[i]; |
| 280 | + |
| 281 | + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver)) |
| 282 | continue; |
| 283 | - if (SSB_WARN_ON(!drv->resume)) |
| 284 | + sdrv = drv_to_ssb_drv(sdev->dev->driver); |
| 285 | + if (SSB_WARN_ON(!sdrv || !sdrv->probe)) |
| 286 | continue; |
| 287 | - err = drv->resume(dev); |
| 288 | + |
| 289 | + err = sdrv->probe(sdev, &sdev->id); |
| 290 | if (err) { |
| 291 | ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n", |
| 292 | - dev_name(dev->dev)); |
| 293 | + dev_name(sdev->dev)); |
| 294 | + result = err; |
| 295 | } |
| 296 | + ssb_driver_put(sdrv); |
| 297 | + ssb_device_put(sdev); |
| 298 | } |
| 299 | |
| 300 | - return 0; |
| 301 | + return result; |
| 302 | } |
| 303 | #endif /* CONFIG_SSB_SPROM */ |
| 304 | |
| 305 | @@ -490,8 +495,7 @@ static int ssb_devices_register(struct s |
| 306 | #endif |
| 307 | break; |
| 308 | case SSB_BUSTYPE_SDIO: |
| 309 | -#ifdef CONFIG_SSB_SDIO |
| 310 | - sdev->irq = bus->host_sdio->dev.irq; |
| 311 | +#ifdef CONFIG_SSB_SDIOHOST |
| 312 | dev->parent = &bus->host_sdio->dev; |
| 313 | #endif |
| 314 | break; |
| 315 | @@ -830,6 +834,9 @@ int ssb_bus_pcibus_register(struct ssb_b |
| 316 | if (!err) { |
| 317 | ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " |
| 318 | "PCI device %s\n", dev_name(&host_pci->dev)); |
| 319 | + } else { |
| 320 | + ssb_printk(KERN_ERR PFX "Failed to register PCI version" |
| 321 | + " of SSB with error %d\n", err); |
| 322 | } |
| 323 | |
| 324 | return err; |
| 325 | --- a/drivers/ssb/pci.c |
| 326 | +++ b/drivers/ssb/pci.c |
| 327 | @@ -17,6 +17,7 @@ |
| 328 | |
| 329 | #include <linux/ssb/ssb.h> |
| 330 | #include <linux/ssb/ssb_regs.h> |
| 331 | +#include <linux/slab.h> |
| 332 | #include <linux/pci.h> |
| 333 | #include <linux/delay.h> |
| 334 | |
| 335 | @@ -167,7 +168,7 @@ err_pci: |
| 336 | } |
| 337 | |
| 338 | /* Get the word-offset for a SSB_SPROM_XXX define. */ |
| 339 | -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE1) / sizeof(u16)) |
| 340 | +#define SPOFF(offset) ((offset) / sizeof(u16)) |
| 341 | /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */ |
| 342 | #define SPEX16(_outvar, _offset, _mask, _shift) \ |
| 343 | out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift)) |
| 344 | --- a/drivers/ssb/pcihost_wrapper.c |
| 345 | +++ b/drivers/ssb/pcihost_wrapper.c |
| 346 | @@ -12,6 +12,7 @@ |
| 347 | */ |
| 348 | |
| 349 | #include <linux/pci.h> |
| 350 | +#include <linux/slab.h> |
| 351 | #include <linux/ssb/ssb.h> |
| 352 | |
| 353 | |
| 354 | --- a/drivers/ssb/pcmcia.c |
| 355 | +++ b/drivers/ssb/pcmcia.c |
| 356 | @@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co |
| 357 | } \ |
| 358 | } while (0) |
| 359 | |
| 360 | -int ssb_pcmcia_get_invariants(struct ssb_bus *bus, |
| 361 | - struct ssb_init_invariants *iv) |
| 362 | +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev, |
| 363 | + tuple_t *tuple, |
| 364 | + void *priv) |
| 365 | { |
| 366 | - tuple_t tuple; |
| 367 | - int res; |
| 368 | - unsigned char buf[32]; |
| 369 | + struct ssb_sprom *sprom = priv; |
| 370 | + |
| 371 | + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID) |
| 372 | + return -EINVAL; |
| 373 | + if (tuple->TupleDataLen != ETH_ALEN + 2) |
| 374 | + return -EINVAL; |
| 375 | + if (tuple->TupleData[1] != ETH_ALEN) |
| 376 | + return -EINVAL; |
| 377 | + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN); |
| 378 | + return 0; |
| 379 | +}; |
| 380 | + |
| 381 | +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev, |
| 382 | + tuple_t *tuple, |
| 383 | + void *priv) |
| 384 | +{ |
| 385 | + struct ssb_init_invariants *iv = priv; |
| 386 | struct ssb_sprom *sprom = &iv->sprom; |
| 387 | struct ssb_boardinfo *bi = &iv->boardinfo; |
| 388 | const char *error_description; |
| 389 | |
| 390 | + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1"); |
| 391 | + switch (tuple->TupleData[0]) { |
| 392 | + case SSB_PCMCIA_CIS_ID: |
| 393 | + GOTO_ERROR_ON((tuple->TupleDataLen != 5) && |
| 394 | + (tuple->TupleDataLen != 7), |
| 395 | + "id tpl size"); |
| 396 | + bi->vendor = tuple->TupleData[1] | |
| 397 | + ((u16)tuple->TupleData[2] << 8); |
| 398 | + break; |
| 399 | + case SSB_PCMCIA_CIS_BOARDREV: |
| 400 | + GOTO_ERROR_ON(tuple->TupleDataLen != 2, |
| 401 | + "boardrev tpl size"); |
| 402 | + sprom->board_rev = tuple->TupleData[1]; |
| 403 | + break; |
| 404 | + case SSB_PCMCIA_CIS_PA: |
| 405 | + GOTO_ERROR_ON((tuple->TupleDataLen != 9) && |
| 406 | + (tuple->TupleDataLen != 10), |
| 407 | + "pa tpl size"); |
| 408 | + sprom->pa0b0 = tuple->TupleData[1] | |
| 409 | + ((u16)tuple->TupleData[2] << 8); |
| 410 | + sprom->pa0b1 = tuple->TupleData[3] | |
| 411 | + ((u16)tuple->TupleData[4] << 8); |
| 412 | + sprom->pa0b2 = tuple->TupleData[5] | |
| 413 | + ((u16)tuple->TupleData[6] << 8); |
| 414 | + sprom->itssi_a = tuple->TupleData[7]; |
| 415 | + sprom->itssi_bg = tuple->TupleData[7]; |
| 416 | + sprom->maxpwr_a = tuple->TupleData[8]; |
| 417 | + sprom->maxpwr_bg = tuple->TupleData[8]; |
| 418 | + break; |
| 419 | + case SSB_PCMCIA_CIS_OEMNAME: |
| 420 | + /* We ignore this. */ |
| 421 | + break; |
| 422 | + case SSB_PCMCIA_CIS_CCODE: |
| 423 | + GOTO_ERROR_ON(tuple->TupleDataLen != 2, |
| 424 | + "ccode tpl size"); |
| 425 | + sprom->country_code = tuple->TupleData[1]; |
| 426 | + break; |
| 427 | + case SSB_PCMCIA_CIS_ANTENNA: |
| 428 | + GOTO_ERROR_ON(tuple->TupleDataLen != 2, |
| 429 | + "ant tpl size"); |
| 430 | + sprom->ant_available_a = tuple->TupleData[1]; |
| 431 | + sprom->ant_available_bg = tuple->TupleData[1]; |
| 432 | + break; |
| 433 | + case SSB_PCMCIA_CIS_ANTGAIN: |
| 434 | + GOTO_ERROR_ON(tuple->TupleDataLen != 2, |
| 435 | + "antg tpl size"); |
| 436 | + sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1]; |
| 437 | + sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1]; |
| 438 | + sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1]; |
| 439 | + sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1]; |
| 440 | + sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1]; |
| 441 | + sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1]; |
| 442 | + sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1]; |
| 443 | + sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1]; |
| 444 | + break; |
| 445 | + case SSB_PCMCIA_CIS_BFLAGS: |
| 446 | + GOTO_ERROR_ON((tuple->TupleDataLen != 3) && |
| 447 | + (tuple->TupleDataLen != 5), |
| 448 | + "bfl tpl size"); |
| 449 | + sprom->boardflags_lo = tuple->TupleData[1] | |
| 450 | + ((u16)tuple->TupleData[2] << 8); |
| 451 | + break; |
| 452 | + case SSB_PCMCIA_CIS_LEDS: |
| 453 | + GOTO_ERROR_ON(tuple->TupleDataLen != 5, |
| 454 | + "leds tpl size"); |
| 455 | + sprom->gpio0 = tuple->TupleData[1]; |
| 456 | + sprom->gpio1 = tuple->TupleData[2]; |
| 457 | + sprom->gpio2 = tuple->TupleData[3]; |
| 458 | + sprom->gpio3 = tuple->TupleData[4]; |
| 459 | + break; |
| 460 | + } |
| 461 | + return -ENOSPC; /* continue with next entry */ |
| 462 | + |
| 463 | +error: |
| 464 | + ssb_printk(KERN_ERR PFX |
| 465 | + "PCMCIA: Failed to fetch device invariants: %s\n", |
| 466 | + error_description); |
| 467 | + return -ENODEV; |
| 468 | +} |
| 469 | + |
| 470 | + |
| 471 | +int ssb_pcmcia_get_invariants(struct ssb_bus *bus, |
| 472 | + struct ssb_init_invariants *iv) |
| 473 | +{ |
| 474 | + struct ssb_sprom *sprom = &iv->sprom; |
| 475 | + int res; |
| 476 | + |
| 477 | memset(sprom, 0xFF, sizeof(*sprom)); |
| 478 | sprom->revision = 1; |
| 479 | sprom->boardflags_lo = 0; |
| 480 | sprom->boardflags_hi = 0; |
| 481 | |
| 482 | /* First fetch the MAC address. */ |
| 483 | - memset(&tuple, 0, sizeof(tuple)); |
| 484 | - tuple.DesiredTuple = CISTPL_FUNCE; |
| 485 | - tuple.TupleData = buf; |
| 486 | - tuple.TupleDataMax = sizeof(buf); |
| 487 | - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple); |
| 488 | - GOTO_ERROR_ON(res != 0, "MAC first tpl"); |
| 489 | - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); |
| 490 | - GOTO_ERROR_ON(res != 0, "MAC first tpl data"); |
| 491 | - while (1) { |
| 492 | - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1"); |
| 493 | - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID) |
| 494 | - break; |
| 495 | - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple); |
| 496 | - GOTO_ERROR_ON(res != 0, "MAC next tpl"); |
| 497 | - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); |
| 498 | - GOTO_ERROR_ON(res != 0, "MAC next tpl data"); |
| 499 | + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE, |
| 500 | + ssb_pcmcia_get_mac, sprom); |
| 501 | + if (res != 0) { |
| 502 | + ssb_printk(KERN_ERR PFX |
| 503 | + "PCMCIA: Failed to fetch MAC address\n"); |
| 504 | + return -ENODEV; |
| 505 | } |
| 506 | - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size"); |
| 507 | - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN); |
| 508 | |
| 509 | /* Fetch the vendor specific tuples. */ |
| 510 | - memset(&tuple, 0, sizeof(tuple)); |
| 511 | - tuple.DesiredTuple = SSB_PCMCIA_CIS; |
| 512 | - tuple.TupleData = buf; |
| 513 | - tuple.TupleDataMax = sizeof(buf); |
| 514 | - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple); |
| 515 | - GOTO_ERROR_ON(res != 0, "VEN first tpl"); |
| 516 | - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); |
| 517 | - GOTO_ERROR_ON(res != 0, "VEN first tpl data"); |
| 518 | - while (1) { |
| 519 | - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1"); |
| 520 | - switch (tuple.TupleData[0]) { |
| 521 | - case SSB_PCMCIA_CIS_ID: |
| 522 | - GOTO_ERROR_ON((tuple.TupleDataLen != 5) && |
| 523 | - (tuple.TupleDataLen != 7), |
| 524 | - "id tpl size"); |
| 525 | - bi->vendor = tuple.TupleData[1] | |
| 526 | - ((u16)tuple.TupleData[2] << 8); |
| 527 | - break; |
| 528 | - case SSB_PCMCIA_CIS_BOARDREV: |
| 529 | - GOTO_ERROR_ON(tuple.TupleDataLen != 2, |
| 530 | - "boardrev tpl size"); |
| 531 | - sprom->board_rev = tuple.TupleData[1]; |
| 532 | - break; |
| 533 | - case SSB_PCMCIA_CIS_PA: |
| 534 | - GOTO_ERROR_ON((tuple.TupleDataLen != 9) && |
| 535 | - (tuple.TupleDataLen != 10), |
| 536 | - "pa tpl size"); |
| 537 | - sprom->pa0b0 = tuple.TupleData[1] | |
| 538 | - ((u16)tuple.TupleData[2] << 8); |
| 539 | - sprom->pa0b1 = tuple.TupleData[3] | |
| 540 | - ((u16)tuple.TupleData[4] << 8); |
| 541 | - sprom->pa0b2 = tuple.TupleData[5] | |
| 542 | - ((u16)tuple.TupleData[6] << 8); |
| 543 | - sprom->itssi_a = tuple.TupleData[7]; |
| 544 | - sprom->itssi_bg = tuple.TupleData[7]; |
| 545 | - sprom->maxpwr_a = tuple.TupleData[8]; |
| 546 | - sprom->maxpwr_bg = tuple.TupleData[8]; |
| 547 | - break; |
| 548 | - case SSB_PCMCIA_CIS_OEMNAME: |
| 549 | - /* We ignore this. */ |
| 550 | - break; |
| 551 | - case SSB_PCMCIA_CIS_CCODE: |
| 552 | - GOTO_ERROR_ON(tuple.TupleDataLen != 2, |
| 553 | - "ccode tpl size"); |
| 554 | - sprom->country_code = tuple.TupleData[1]; |
| 555 | - break; |
| 556 | - case SSB_PCMCIA_CIS_ANTENNA: |
| 557 | - GOTO_ERROR_ON(tuple.TupleDataLen != 2, |
| 558 | - "ant tpl size"); |
| 559 | - sprom->ant_available_a = tuple.TupleData[1]; |
| 560 | - sprom->ant_available_bg = tuple.TupleData[1]; |
| 561 | - break; |
| 562 | - case SSB_PCMCIA_CIS_ANTGAIN: |
| 563 | - GOTO_ERROR_ON(tuple.TupleDataLen != 2, |
| 564 | - "antg tpl size"); |
| 565 | - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1]; |
| 566 | - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1]; |
| 567 | - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1]; |
| 568 | - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1]; |
| 569 | - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1]; |
| 570 | - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1]; |
| 571 | - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1]; |
| 572 | - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1]; |
| 573 | - break; |
| 574 | - case SSB_PCMCIA_CIS_BFLAGS: |
| 575 | - GOTO_ERROR_ON((tuple.TupleDataLen != 3) && |
| 576 | - (tuple.TupleDataLen != 5), |
| 577 | - "bfl tpl size"); |
| 578 | - sprom->boardflags_lo = tuple.TupleData[1] | |
| 579 | - ((u16)tuple.TupleData[2] << 8); |
| 580 | - break; |
| 581 | - case SSB_PCMCIA_CIS_LEDS: |
| 582 | - GOTO_ERROR_ON(tuple.TupleDataLen != 5, |
| 583 | - "leds tpl size"); |
| 584 | - sprom->gpio0 = tuple.TupleData[1]; |
| 585 | - sprom->gpio1 = tuple.TupleData[2]; |
| 586 | - sprom->gpio2 = tuple.TupleData[3]; |
| 587 | - sprom->gpio3 = tuple.TupleData[4]; |
| 588 | - break; |
| 589 | - } |
| 590 | - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple); |
| 591 | - if (res == -ENOSPC) |
| 592 | - break; |
| 593 | - GOTO_ERROR_ON(res != 0, "VEN next tpl"); |
| 594 | - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); |
| 595 | - GOTO_ERROR_ON(res != 0, "VEN next tpl data"); |
| 596 | - } |
| 597 | + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS, |
| 598 | + ssb_pcmcia_do_get_invariants, sprom); |
| 599 | + if ((res == 0) || (res == -ENOSPC)) |
| 600 | + return 0; |
| 601 | |
| 602 | - return 0; |
| 603 | -error: |
| 604 | ssb_printk(KERN_ERR PFX |
| 605 | - "PCMCIA: Failed to fetch device invariants: %s\n", |
| 606 | - error_description); |
| 607 | + "PCMCIA: Failed to fetch device invariants\n"); |
| 608 | return -ENODEV; |
| 609 | } |
| 610 | |
| 611 | --- a/drivers/ssb/scan.c |
| 612 | +++ b/drivers/ssb/scan.c |
| 613 | @@ -354,7 +354,7 @@ int ssb_bus_scan(struct ssb_bus *bus, |
| 614 | dev->bus = bus; |
| 615 | dev->ops = bus->ops; |
| 616 | |
| 617 | - ssb_dprintk(KERN_INFO PFX |
| 618 | + printk(KERN_DEBUG PFX |
| 619 | "Core %d found: %s " |
| 620 | "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n", |
| 621 | i, ssb_core_name(dev->id.coreid), |
| 622 | --- a/drivers/ssb/sprom.c |
| 623 | +++ b/drivers/ssb/sprom.c |
| 624 | @@ -14,6 +14,7 @@ |
| 625 | #include "ssb_private.h" |
| 626 | |
| 627 | #include <linux/ctype.h> |
| 628 | +#include <linux/slab.h> |
| 629 | |
| 630 | |
| 631 | static const struct ssb_sprom *fallback_sprom; |
| 632 | @@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_ |
| 633 | u16 *sprom; |
| 634 | int res = 0, err = -ENOMEM; |
| 635 | size_t sprom_size_words = bus->sprom_size; |
| 636 | + struct ssb_freeze_context freeze; |
| 637 | |
| 638 | sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL); |
| 639 | if (!sprom) |
| 640 | @@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_ |
| 641 | err = -ERESTARTSYS; |
| 642 | if (mutex_lock_interruptible(&bus->sprom_mutex)) |
| 643 | goto out_kfree; |
| 644 | - err = ssb_devices_freeze(bus); |
| 645 | - if (err == -EOPNOTSUPP) { |
| 646 | - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. " |
| 647 | - "No suspend support. Is CONFIG_PM enabled?\n"); |
| 648 | - goto out_unlock; |
| 649 | - } |
| 650 | + err = ssb_devices_freeze(bus, &freeze); |
| 651 | if (err) { |
| 652 | ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n"); |
| 653 | goto out_unlock; |
| 654 | } |
| 655 | res = sprom_write(bus, sprom); |
| 656 | - err = ssb_devices_thaw(bus); |
| 657 | + err = ssb_devices_thaw(&freeze); |
| 658 | if (err) |
| 659 | ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n"); |
| 660 | out_unlock: |
| 661 | --- a/drivers/ssb/ssb_private.h |
| 662 | +++ b/drivers/ssb/ssb_private.h |
| 663 | @@ -176,19 +176,27 @@ extern const struct ssb_sprom *ssb_get_f |
| 664 | |
| 665 | /* core.c */ |
| 666 | extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m); |
| 667 | -extern int ssb_devices_freeze(struct ssb_bus *bus); |
| 668 | -extern int ssb_devices_thaw(struct ssb_bus *bus); |
| 669 | extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev); |
| 670 | int ssb_for_each_bus_call(unsigned long data, |
| 671 | int (*func)(struct ssb_bus *bus, unsigned long data)); |
| 672 | extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev); |
| 673 | |
| 674 | +struct ssb_freeze_context { |
| 675 | + /* Pointer to the bus */ |
| 676 | + struct ssb_bus *bus; |
| 677 | + /* Boolean list to indicate whether a device is frozen on this bus. */ |
| 678 | + bool device_frozen[SSB_MAX_NR_CORES]; |
| 679 | +}; |
| 680 | +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx); |
| 681 | +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx); |
| 682 | + |
| 683 | + |
| 684 | |
| 685 | /* b43_pci_bridge.c */ |
| 686 | #ifdef CONFIG_SSB_B43_PCI_BRIDGE |
| 687 | extern int __init b43_pci_ssb_bridge_init(void); |
| 688 | extern void __exit b43_pci_ssb_bridge_exit(void); |
| 689 | -#else /* CONFIG_SSB_B43_PCI_BRIDGR */ |
| 690 | +#else /* CONFIG_SSB_B43_PCI_BRIDGE */ |
| 691 | static inline int b43_pci_ssb_bridge_init(void) |
| 692 | { |
| 693 | return 0; |
| 694 | @@ -196,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini |
| 695 | static inline void b43_pci_ssb_bridge_exit(void) |
| 696 | { |
| 697 | } |
| 698 | -#endif /* CONFIG_SSB_PCIHOST */ |
| 699 | +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */ |
| 700 | |
| 701 | #endif /* LINUX_SSB_PRIVATE_H_ */ |
| 702 | --- a/include/linux/ssb/ssb.h |
| 703 | +++ b/include/linux/ssb/ssb.h |
| 704 | @@ -269,7 +269,8 @@ struct ssb_bus { |
| 705 | |
| 706 | const struct ssb_bus_ops *ops; |
| 707 | |
| 708 | - /* The core in the basic address register window. (PCI bus only) */ |
| 709 | + /* The core currently mapped into the MMIO window. |
| 710 | + * Not valid on all host-buses. So don't use outside of SSB. */ |
| 711 | struct ssb_device *mapped_device; |
| 712 | union { |
| 713 | /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */ |
| 714 | @@ -281,14 +282,17 @@ struct ssb_bus { |
| 715 | * On PCMCIA-host busses this is used to protect the whole MMIO access. */ |
| 716 | spinlock_t bar_lock; |
| 717 | |
| 718 | - /* The bus this backplane is running on. */ |
| 719 | + /* The host-bus this backplane is running on. */ |
| 720 | enum ssb_bustype bustype; |
| 721 | - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */ |
| 722 | - struct pci_dev *host_pci; |
| 723 | - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */ |
| 724 | - struct pcmcia_device *host_pcmcia; |
| 725 | - /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */ |
| 726 | - struct sdio_func *host_sdio; |
| 727 | + /* Pointers to the host-bus. Check bustype before using any of these pointers. */ |
| 728 | + union { |
| 729 | + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */ |
| 730 | + struct pci_dev *host_pci; |
| 731 | + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */ |
| 732 | + struct pcmcia_device *host_pcmcia; |
| 733 | + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */ |
| 734 | + struct sdio_func *host_sdio; |
| 735 | + }; |
| 736 | |
| 737 | /* See enum ssb_quirks */ |
| 738 | unsigned int quirks; |
| 739 | --- a/include/linux/ssb/ssb_regs.h |
| 740 | +++ b/include/linux/ssb/ssb_regs.h |
| 741 | @@ -172,25 +172,25 @@ |
| 742 | #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16)) |
| 743 | #define SSB_SPROM_BASE1 0x1000 |
| 744 | #define SSB_SPROM_BASE31 0x0800 |
| 745 | -#define SSB_SPROM_REVISION 0x107E |
| 746 | +#define SSB_SPROM_REVISION 0x007E |
| 747 | #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ |
| 748 | #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */ |
| 749 | #define SSB_SPROM_REVISION_CRC_SHIFT 8 |
| 750 | |
| 751 | /* SPROM Revision 1 */ |
| 752 | -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */ |
| 753 | -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */ |
| 754 | -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */ |
| 755 | -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */ |
| 756 | -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */ |
| 757 | -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */ |
| 758 | -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */ |
| 759 | +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */ |
| 760 | +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */ |
| 761 | +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */ |
| 762 | +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */ |
| 763 | +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */ |
| 764 | +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */ |
| 765 | +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */ |
| 766 | #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ |
| 767 | #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ |
| 768 | #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5 |
| 769 | #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ |
| 770 | #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ |
| 771 | -#define SSB_SPROM1_BINF 0x105C /* Board info */ |
| 772 | +#define SSB_SPROM1_BINF 0x005C /* Board info */ |
| 773 | #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */ |
| 774 | #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */ |
| 775 | #define SSB_SPROM1_BINF_CCODE_SHIFT 8 |
| 776 | @@ -198,63 +198,63 @@ |
| 777 | #define SSB_SPROM1_BINF_ANTBG_SHIFT 12 |
| 778 | #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */ |
| 779 | #define SSB_SPROM1_BINF_ANTA_SHIFT 14 |
| 780 | -#define SSB_SPROM1_PA0B0 0x105E |
| 781 | -#define SSB_SPROM1_PA0B1 0x1060 |
| 782 | -#define SSB_SPROM1_PA0B2 0x1062 |
| 783 | -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */ |
| 784 | +#define SSB_SPROM1_PA0B0 0x005E |
| 785 | +#define SSB_SPROM1_PA0B1 0x0060 |
| 786 | +#define SSB_SPROM1_PA0B2 0x0062 |
| 787 | +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */ |
| 788 | #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */ |
| 789 | #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 790 | #define SSB_SPROM1_GPIOA_P1_SHIFT 8 |
| 791 | -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */ |
| 792 | +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */ |
| 793 | #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */ |
| 794 | #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 795 | #define SSB_SPROM1_GPIOB_P3_SHIFT 8 |
| 796 | -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */ |
| 797 | +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */ |
| 798 | #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */ |
| 799 | #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */ |
| 800 | #define SSB_SPROM1_MAXPWR_A_SHIFT 8 |
| 801 | -#define SSB_SPROM1_PA1B0 0x106A |
| 802 | -#define SSB_SPROM1_PA1B1 0x106C |
| 803 | -#define SSB_SPROM1_PA1B2 0x106E |
| 804 | -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */ |
| 805 | +#define SSB_SPROM1_PA1B0 0x006A |
| 806 | +#define SSB_SPROM1_PA1B1 0x006C |
| 807 | +#define SSB_SPROM1_PA1B2 0x006E |
| 808 | +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */ |
| 809 | #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/ |
| 810 | #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */ |
| 811 | #define SSB_SPROM1_ITSSI_A_SHIFT 8 |
| 812 | -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */ |
| 813 | -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */ |
| 814 | +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */ |
| 815 | +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */ |
| 816 | #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */ |
| 817 | #define SSB_SPROM1_AGAIN_BG_SHIFT 0 |
| 818 | #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */ |
| 819 | #define SSB_SPROM1_AGAIN_A_SHIFT 8 |
| 820 | |
| 821 | /* SPROM Revision 2 (inherits from rev 1) */ |
| 822 | -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */ |
| 823 | -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */ |
| 824 | +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */ |
| 825 | +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */ |
| 826 | #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */ |
| 827 | #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */ |
| 828 | #define SSB_SPROM2_MAXP_A_LO_SHIFT 8 |
| 829 | -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */ |
| 830 | -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */ |
| 831 | -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */ |
| 832 | -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */ |
| 833 | -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */ |
| 834 | -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */ |
| 835 | -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */ |
| 836 | +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */ |
| 837 | +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */ |
| 838 | +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */ |
| 839 | +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */ |
| 840 | +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */ |
| 841 | +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */ |
| 842 | +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */ |
| 843 | #define SSB_SPROM2_OPO_VALUE 0x00FF |
| 844 | #define SSB_SPROM2_OPO_UNUSED 0xFF00 |
| 845 | -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */ |
| 846 | +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */ |
| 847 | |
| 848 | /* SPROM Revision 3 (inherits most data from rev 2) */ |
| 849 | -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */ |
| 850 | -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ |
| 851 | -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ |
| 852 | -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ |
| 853 | -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ |
| 854 | +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ |
| 855 | +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ |
| 856 | +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ |
| 857 | +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ |
| 858 | #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */ |
| 859 | #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8 |
| 860 | #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */ |
| 861 | #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16 |
| 862 | -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */ |
| 863 | +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */ |
| 864 | +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */ |
| 865 | #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ |
| 866 | #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ |
| 867 | #define SSB_SPROM3_CCKPO_2M_SHIFT 4 |
| 868 | @@ -265,100 +265,100 @@ |
| 869 | #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ |
| 870 | |
| 871 | /* SPROM Revision 4 */ |
| 872 | -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */ |
| 873 | -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */ |
| 874 | +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */ |
| 875 | +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */ |
| 876 | +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */ |
| 877 | +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */ |
| 878 | +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */ |
| 879 | +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ |
| 880 | +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 881 | +#define SSB_SPROM4_GPIOA_P1_SHIFT 8 |
| 882 | +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */ |
| 883 | +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ |
| 884 | +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 885 | +#define SSB_SPROM4_GPIOB_P3_SHIFT 8 |
| 886 | +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */ |
| 887 | #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ |
| 888 | #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ |
| 889 | #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 |
| 890 | #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ |
| 891 | #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ |
| 892 | -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */ |
| 893 | -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */ |
| 894 | -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ |
| 895 | -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 |
| 896 | -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ |
| 897 | -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 |
| 898 | -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */ |
| 899 | -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */ |
| 900 | +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ |
| 901 | +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ |
| 902 | +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 |
| 903 | +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ |
| 904 | +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 |
| 905 | +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ |
| 906 | #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ |
| 907 | #define SSB_SPROM4_AGAIN0_SHIFT 0 |
| 908 | #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */ |
| 909 | #define SSB_SPROM4_AGAIN1_SHIFT 8 |
| 910 | -#define SSB_SPROM4_AGAIN23 0x1060 |
| 911 | +#define SSB_SPROM4_AGAIN23 0x0060 |
| 912 | #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */ |
| 913 | #define SSB_SPROM4_AGAIN2_SHIFT 0 |
| 914 | #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */ |
| 915 | #define SSB_SPROM4_AGAIN3_SHIFT 8 |
| 916 | -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */ |
| 917 | -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */ |
| 918 | +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */ |
| 919 | #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ |
| 920 | #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
| 921 | #define SSB_SPROM4_ITSSI_BG_SHIFT 8 |
| 922 | -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */ |
| 923 | +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */ |
| 924 | #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */ |
| 925 | #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ |
| 926 | #define SSB_SPROM4_ITSSI_A_SHIFT 8 |
| 927 | -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */ |
| 928 | -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ |
| 929 | -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 930 | -#define SSB_SPROM4_GPIOA_P1_SHIFT 8 |
| 931 | -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */ |
| 932 | -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ |
| 933 | -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 934 | -#define SSB_SPROM4_GPIOB_P3_SHIFT 8 |
| 935 | -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */ |
| 936 | -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */ |
| 937 | -#define SSB_SPROM4_PA0B2 0x1086 |
| 938 | -#define SSB_SPROM4_PA1B0 0x108E |
| 939 | -#define SSB_SPROM4_PA1B1 0x1090 |
| 940 | -#define SSB_SPROM4_PA1B2 0x1092 |
| 941 | +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */ |
| 942 | +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */ |
| 943 | +#define SSB_SPROM4_PA0B2 0x0086 |
| 944 | +#define SSB_SPROM4_PA1B0 0x008E |
| 945 | +#define SSB_SPROM4_PA1B1 0x0090 |
| 946 | +#define SSB_SPROM4_PA1B2 0x0092 |
| 947 | |
| 948 | /* SPROM Revision 5 (inherits most data from rev 4) */ |
| 949 | -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */ |
| 950 | -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */ |
| 951 | -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */ |
| 952 | -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */ |
| 953 | -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */ |
| 954 | +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */ |
| 955 | +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */ |
| 956 | +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */ |
| 957 | +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */ |
| 958 | +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */ |
| 959 | #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */ |
| 960 | #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 961 | #define SSB_SPROM5_GPIOA_P1_SHIFT 8 |
| 962 | -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */ |
| 963 | +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */ |
| 964 | #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */ |
| 965 | #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 966 | #define SSB_SPROM5_GPIOB_P3_SHIFT 8 |
| 967 | |
| 968 | /* SPROM Revision 8 */ |
| 969 | -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */ |
| 970 | -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */ |
| 971 | -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */ |
| 972 | -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */ |
| 973 | -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */ |
| 974 | -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */ |
| 975 | -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */ |
| 976 | -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/ |
| 977 | -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ |
| 978 | -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 |
| 979 | -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ |
| 980 | -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 |
| 981 | -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */ |
| 982 | +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */ |
| 983 | +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */ |
| 984 | +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */ |
| 985 | +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */ |
| 986 | +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */ |
| 987 | +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */ |
| 988 | +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */ |
| 989 | +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */ |
| 990 | +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ |
| 991 | +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 992 | +#define SSB_SPROM8_GPIOA_P1_SHIFT 8 |
| 993 | +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */ |
| 994 | +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ |
| 995 | +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 996 | +#define SSB_SPROM8_GPIOB_P3_SHIFT 8 |
| 997 | +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/ |
| 998 | +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ |
| 999 | +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 |
| 1000 | +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ |
| 1001 | +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 |
| 1002 | +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */ |
| 1003 | #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */ |
| 1004 | #define SSB_SPROM8_AGAIN0_SHIFT 0 |
| 1005 | #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */ |
| 1006 | #define SSB_SPROM8_AGAIN1_SHIFT 8 |
| 1007 | -#define SSB_SPROM8_AGAIN23 0x10A0 |
| 1008 | +#define SSB_SPROM8_AGAIN23 0x00A0 |
| 1009 | #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */ |
| 1010 | #define SSB_SPROM8_AGAIN2_SHIFT 0 |
| 1011 | #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */ |
| 1012 | #define SSB_SPROM8_AGAIN3_SHIFT 8 |
| 1013 | -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */ |
| 1014 | -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ |
| 1015 | -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 1016 | -#define SSB_SPROM8_GPIOA_P1_SHIFT 8 |
| 1017 | -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */ |
| 1018 | -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ |
| 1019 | -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 1020 | -#define SSB_SPROM8_GPIOB_P3_SHIFT 8 |
| 1021 | -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */ |
| 1022 | +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */ |
| 1023 | #define SSB_SPROM8_RSSISMF2G 0x000F |
| 1024 | #define SSB_SPROM8_RSSISMC2G 0x00F0 |
| 1025 | #define SSB_SPROM8_RSSISMC2G_SHIFT 4 |
| 1026 | @@ -366,7 +366,7 @@ |
| 1027 | #define SSB_SPROM8_RSSISAV2G_SHIFT 8 |
| 1028 | #define SSB_SPROM8_BXA2G 0x1800 |
| 1029 | #define SSB_SPROM8_BXA2G_SHIFT 11 |
| 1030 | -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */ |
| 1031 | +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */ |
| 1032 | #define SSB_SPROM8_RSSISMF5G 0x000F |
| 1033 | #define SSB_SPROM8_RSSISMC5G 0x00F0 |
| 1034 | #define SSB_SPROM8_RSSISMC5G_SHIFT 4 |
| 1035 | @@ -374,47 +374,47 @@ |
| 1036 | #define SSB_SPROM8_RSSISAV5G_SHIFT 8 |
| 1037 | #define SSB_SPROM8_BXA5G 0x1800 |
| 1038 | #define SSB_SPROM8_BXA5G_SHIFT 11 |
| 1039 | -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */ |
| 1040 | +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */ |
| 1041 | #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */ |
| 1042 | #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */ |
| 1043 | #define SSB_SPROM8_TRI5G_SHIFT 8 |
| 1044 | -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */ |
| 1045 | +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */ |
| 1046 | #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */ |
| 1047 | #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */ |
| 1048 | #define SSB_SPROM8_TRI5GH_SHIFT 8 |
| 1049 | -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */ |
| 1050 | +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */ |
| 1051 | #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */ |
| 1052 | #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ |
| 1053 | #define SSB_SPROM8_RXPO5G_SHIFT 8 |
| 1054 | -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */ |
| 1055 | +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */ |
| 1056 | #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ |
| 1057 | #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
| 1058 | #define SSB_SPROM8_ITSSI_BG_SHIFT 8 |
| 1059 | -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */ |
| 1060 | -#define SSB_SPROM8_PA0B1 0x10C4 |
| 1061 | -#define SSB_SPROM8_PA0B2 0x10C6 |
| 1062 | -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */ |
| 1063 | +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */ |
| 1064 | +#define SSB_SPROM8_PA0B1 0x00C4 |
| 1065 | +#define SSB_SPROM8_PA0B2 0x00C6 |
| 1066 | +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */ |
| 1067 | #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */ |
| 1068 | #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ |
| 1069 | #define SSB_SPROM8_ITSSI_A_SHIFT 8 |
| 1070 | -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */ |
| 1071 | +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */ |
| 1072 | #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */ |
| 1073 | #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */ |
| 1074 | #define SSB_SPROM8_MAXP_AL_SHIFT 8 |
| 1075 | -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */ |
| 1076 | -#define SSB_SPROM8_PA1B1 0x10CE |
| 1077 | -#define SSB_SPROM8_PA1B2 0x10D0 |
| 1078 | -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */ |
| 1079 | -#define SSB_SPROM8_PA1LOB1 0x10D4 |
| 1080 | -#define SSB_SPROM8_PA1LOB2 0x10D6 |
| 1081 | -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */ |
| 1082 | -#define SSB_SPROM8_PA1HIB1 0x10DA |
| 1083 | -#define SSB_SPROM8_PA1HIB2 0x10DC |
| 1084 | -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */ |
| 1085 | -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */ |
| 1086 | -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */ |
| 1087 | -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */ |
| 1088 | -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */ |
| 1089 | +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */ |
| 1090 | +#define SSB_SPROM8_PA1B1 0x00CE |
| 1091 | +#define SSB_SPROM8_PA1B2 0x00D0 |
| 1092 | +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */ |
| 1093 | +#define SSB_SPROM8_PA1LOB1 0x00D4 |
| 1094 | +#define SSB_SPROM8_PA1LOB2 0x00D6 |
| 1095 | +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */ |
| 1096 | +#define SSB_SPROM8_PA1HIB1 0x00DA |
| 1097 | +#define SSB_SPROM8_PA1HIB2 0x00DC |
| 1098 | +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */ |
| 1099 | +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */ |
| 1100 | +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */ |
| 1101 | +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */ |
| 1102 | +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */ |
| 1103 | |
| 1104 | /* Values for SSB_SPROM1_BINF_CCODE */ |
| 1105 | enum { |
| 1106 | |
