| 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify |
| 3 | * it under the terms of the GNU General Public License as published by |
| 4 | * the Free Software Foundation; either version 2 of the License, or |
| 5 | * (at your option) any later version. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | * You should have received a copy of the GNU General Public License |
| 13 | * along with this program; if not, write to the Free Software |
| 14 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
| 15 | * |
| 16 | * Copyright (C) 2007 John Crispin <blogic@openwrt.org> |
| 17 | */ |
| 18 | |
| 19 | #ifndef _IFXMIPS_CGU_H__ |
| 20 | #define _IFXMIPS_CGU_H__ |
| 21 | |
| 22 | #define BASIC_INPUT_CLOCK_FREQUENCY_1 35328000 |
| 23 | #define BASIC_INPUT_CLOCK_FREQUENCY_2 36000000 |
| 24 | |
| 25 | #define BASIS_INPUT_CRYSTAL_USB 12000000 |
| 26 | |
| 27 | #define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) |
| 28 | |
| 29 | #define CGU_PLL0_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 31)) |
| 30 | #define CGU_PLL0_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 30)) |
| 31 | #define CGU_PLL0_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 28)) |
| 32 | #define CGU_PLL0_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 27)) |
| 33 | #define CGU_PLL1_SRC (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 31)) |
| 34 | #define CGU_PLL1_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 30)) |
| 35 | #define CGU_PLL1_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 28)) |
| 36 | #define CGU_PLL1_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 27)) |
| 37 | #define CGU_PLL2_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 20)) |
| 38 | #define CGU_PLL2_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 19)) |
| 39 | #define CGU_SYS_FPI_SEL (1 << 6) |
| 40 | #define CGU_SYS_DDR_SEL 0x3 |
| 41 | #define CGU_PLL0_SRC (1 << 29) |
| 42 | |
| 43 | #define CGU_PLL0_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17) |
| 44 | #define CGU_PLL0_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6) |
| 45 | #define CGU_PLL0_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2) |
| 46 | #define CGU_PLL1_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17) |
| 47 | #define CGU_PLL1_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6) |
| 48 | #define CGU_PLL1_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2) |
| 49 | #define CGU_PLL2_SRC GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17) |
| 50 | #define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13) |
| 51 | #define CGU_PLL2_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6) |
| 52 | #define CGU_PLL2_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2) |
| 53 | #define CGU_IF_CLK_PCI_CLK GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20) |
| 54 | |
| 55 | |
| 56 | unsigned int cgu_get_mips_clock(int cpu); |
| 57 | unsigned int cgu_get_io_region_clock(void); |
| 58 | unsigned int cgu_get_fpi_bus_clock(int fpi); |
| 59 | void cgu_setup_pci_clk(int internal_clock); |
| 60 | unsigned int ifxmips_get_ddr_hz(void); |
| 61 | unsigned int ifxmips_get_fpi_hz(void); |
| 62 | unsigned int ifxmips_get_cpu_hz(void); |
| 63 | |
| 64 | #endif |
| 65 | |
