Root/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_dma.h

1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2005 infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
18 *
19 */
20#ifndef _IFXMIPS_DMA_H__
21#define _IFXMIPS_DMA_H__
22
23#define RCV_INT 1
24#define TX_BUF_FULL_INT 2
25#define TRANSMIT_CPT_INT 4
26#define IFXMIPS_DMA_CH_ON 1
27#define IFXMIPS_DMA_CH_OFF 0
28#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100
29
30enum attr_t{
31    TX = 0,
32    RX = 1,
33    RESERVED = 2,
34    DEFAULT = 3,
35};
36
37#define DMA_OWN 1
38#define CPU_OWN 0
39#define DMA_MAJOR 250
40
41#define DMA_DESC_OWN_CPU 0x0
42#define DMA_DESC_OWN_DMA 0x80000000
43#define DMA_DESC_CPT_SET 0x40000000
44#define DMA_DESC_SOP_SET 0x20000000
45#define DMA_DESC_EOP_SET 0x10000000
46
47#define MISCFG_MASK 0x40
48#define RDERR_MASK 0x20
49#define CHOFF_MASK 0x10
50#define DESCPT_MASK 0x8
51#define DUR_MASK 0x4
52#define EOP_MASK 0x2
53
54#define DMA_DROP_MASK (1<<31)
55
56#define IFXMIPS_DMA_RX -1
57#define IFXMIPS_DMA_TX 1
58
59struct dma_chan_map {
60    const char *dev_name;
61    enum attr_t dir;
62    int pri;
63    int irq;
64    int rel_chan_no;
65};
66
67#ifdef CONFIG_CPU_LITTLE_ENDIAN
68struct rx_desc {
69    u32 data_length:16;
70    volatile u32 reserved:7;
71    volatile u32 byte_offset:2;
72    volatile u32 Burst_length_offset:3;
73    volatile u32 EoP:1;
74    volatile u32 Res:1;
75    volatile u32 C:1;
76    volatile u32 OWN:1;
77    volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
78};
79
80struct tx_desc {
81    volatile u32 data_length:16;
82    volatile u32 reserved1:7;
83    volatile u32 byte_offset:5;
84    volatile u32 EoP:1;
85    volatile u32 SoP:1;
86    volatile u32 C:1;
87    volatile u32 OWN:1;
88    volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
89};
90#else /* BIG */
91struct rx_desc {
92    union {
93        struct {
94            volatile u32 OWN:1;
95            volatile u32 C:1;
96            volatile u32 SoP:1;
97            volatile u32 EoP:1;
98            volatile u32 Burst_length_offset:3;
99            volatile u32 byte_offset:2;
100            volatile u32 reserve:7;
101            volatile u32 data_length:16;
102        } field;
103        volatile u32 word;
104    } status;
105    volatile u32 Data_Pointer;
106};
107
108struct tx_desc {
109    union {
110        struct {
111            volatile u32 OWN:1;
112            volatile u32 C:1;
113            volatile u32 SoP:1;
114            volatile u32 EoP:1;
115            volatile u32 byte_offset:5;
116            volatile u32 reserved:7;
117            volatile u32 data_length:16;
118        } field;
119        volatile u32 word;
120    } status;
121    volatile u32 Data_Pointer;
122};
123#endif /* ENDIAN */
124
125struct dma_channel_info {
126    /* relative channel number */
127    int rel_chan_no;
128    /* class for this channel for QoS */
129    int pri;
130    /* specify byte_offset */
131    int byte_offset;
132    /* direction */
133    int dir;
134    /* irq number */
135    int irq;
136    /* descriptor parameter */
137    int desc_base;
138    int desc_len;
139    int curr_desc;
140    int prev_desc; /* only used if it is a tx channel*/
141    /* weight setting for WFQ algorithm*/
142    int weight;
143    int default_weight;
144    int packet_size;
145    int burst_len;
146    /* on or off of this channel */
147    int control;
148    /* optional information for the upper layer devices */
149#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
150    void *opt[64];
151#else
152    void *opt[25];
153#endif
154    /* Pointer to the peripheral device who is using this channel */
155    void *dma_dev;
156    /* channel operations */
157    void (*open)(struct dma_channel_info *pCh);
158    void (*close)(struct dma_channel_info *pCh);
159    void (*reset)(struct dma_channel_info *pCh);
160    void (*enable_irq)(struct dma_channel_info *pCh);
161    void (*disable_irq)(struct dma_channel_info *pCh);
162};
163
164struct dma_device_info {
165    /* device name of this peripheral */
166    char device_name[15];
167    int reserved;
168    int tx_burst_len;
169    int rx_burst_len;
170    int default_weight;
171    int current_tx_chan;
172    int current_rx_chan;
173    int num_tx_chan;
174    int num_rx_chan;
175    int max_rx_chan_num;
176    int max_tx_chan_num;
177    struct dma_channel_info *tx_chan[20];
178    struct dma_channel_info *rx_chan[20];
179    /*functions, optional*/
180    u8 *(*buffer_alloc)(int len, int *offset, void **opt);
181    void (*buffer_free)(u8 *dataptr, void *opt);
182    int (*intr_handler)(struct dma_device_info *info, int status);
183    void *priv; /* used by peripheral driver only */
184};
185
186struct dma_device_info *dma_device_reserve(char *dev_name);
187void dma_device_release(struct dma_device_info *dev);
188void dma_device_register(struct dma_device_info *info);
189void dma_device_unregister(struct dma_device_info *info);
190int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt);
191int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len,
192    void *opt);
193
194#endif
195
196

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